Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: set gfx clock gating for tonga/polaris.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rex Zhu and committed by
Alex Deucher
a8ca3413 1bb08f91

+77
+77
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 5979 5979 return 0; 5980 5980 } 5981 5981 5982 + static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, 5983 + enum amd_clockgating_state state) 5984 + { 5985 + uint32_t msg_id, pp_state; 5986 + void *pp_handle = adev->powerplay.pp_handle; 5987 + 5988 + if (state == AMD_CG_STATE_UNGATE) 5989 + pp_state = 0; 5990 + else 5991 + pp_state = PP_STATE_CG | PP_STATE_LS; 5992 + 5993 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 5994 + PP_BLOCK_GFX_CG, 5995 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 5996 + pp_state); 5997 + amd_set_clockgating_by_smu(pp_handle, msg_id); 5998 + 5999 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6000 + PP_BLOCK_GFX_MG, 6001 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6002 + pp_state); 6003 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6004 + 6005 + return 0; 6006 + } 6007 + 6008 + static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, 6009 + enum amd_clockgating_state state) 6010 + { 6011 + uint32_t msg_id, pp_state; 6012 + void *pp_handle = adev->powerplay.pp_handle; 6013 + 6014 + if (state == AMD_CG_STATE_UNGATE) 6015 + pp_state = 0; 6016 + else 6017 + pp_state = PP_STATE_CG | PP_STATE_LS; 6018 + 6019 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6020 + PP_BLOCK_GFX_CG, 6021 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6022 + pp_state); 6023 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6024 + 6025 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6026 + PP_BLOCK_GFX_3D, 6027 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6028 + pp_state); 6029 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6030 + 6031 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6032 + PP_BLOCK_GFX_MG, 6033 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6034 + pp_state); 6035 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6036 + 6037 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6038 + PP_BLOCK_GFX_RLC, 6039 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6040 + pp_state); 6041 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6042 + 6043 + msg_id = PP_CG_MSG_ID(PP_GROUP_GFX, 6044 + PP_BLOCK_GFX_CP, 6045 + PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS, 6046 + pp_state); 6047 + amd_set_clockgating_by_smu(pp_handle, msg_id); 6048 + 6049 + return 0; 6050 + } 6051 + 5982 6052 static int gfx_v8_0_set_clockgating_state(void *handle, 5983 6053 enum amd_clockgating_state state) 5984 6054 { ··· 6060 5990 case CHIP_STONEY: 6061 5991 gfx_v8_0_update_gfx_clock_gating(adev, 6062 5992 state == AMD_CG_STATE_GATE ? true : false); 5993 + break; 5994 + case CHIP_TONGA: 5995 + gfx_v8_0_tonga_update_gfx_clock_gating(adev, state); 5996 + break; 5997 + case CHIP_POLARIS10: 5998 + case CHIP_POLARIS11: 5999 + gfx_v8_0_polaris_update_gfx_clock_gating(adev, state); 6063 6000 break; 6064 6001 default: 6065 6002 break;