tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
memory: Add support for Exynos SROM driver
This patch adds Exynos SROM controller driver which will handle
save restore of SROM registers during S2R.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
[p.fedin@samsung.com: tested on SMDK5410]
Tested-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
[k.kozlowski: Minor COMPILE_TEST adjustments in Kconfig entries]
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
authored by
Pankaj Dubey
and committed by
Krzysztof Kozlowski
a8aabb91
92537d65
+242
+1
drivers/memory/Kconfig
+1
drivers/memory/Kconfig
+1
drivers/memory/Makefile
+1
drivers/memory/Makefile
+13
drivers/memory/samsung/Kconfig
+13
drivers/memory/samsung/Kconfig
···
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config SAMSUNG_MC
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bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
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help
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Support for the Memory Controller (MC) devices found on
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Samsung Exynos SoCs.
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if SAMSUNG_MC
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config EXYNOS_SROM
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bool "Exynos SROM controller driver" if COMPILE_TEST
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depends on (ARM && ARCH_EXYNOS && PM) || (COMPILE_TEST && HAS_IOMEM)
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endif
+1
drivers/memory/samsung/Makefile
+1
drivers/memory/samsung/Makefile
···
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obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o
+175
drivers/memory/samsung/exynos-srom.c
+175
drivers/memory/samsung/exynos-srom.c
···
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS - SROM Controller support
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* Author: Pankaj Dubey <pankaj.dubey@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "exynos-srom.h"
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static const unsigned long exynos_srom_offsets[] = {
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/* SROM side */
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EXYNOS_SROM_BW,
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EXYNOS_SROM_BC0,
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EXYNOS_SROM_BC1,
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EXYNOS_SROM_BC2,
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EXYNOS_SROM_BC3,
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};
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/**
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* struct exynos_srom_reg_dump: register dump of SROM Controller registers.
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* @offset: srom register offset from the controller base address.
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* @value: the value of register under the offset.
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*/
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struct exynos_srom_reg_dump {
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u32 offset;
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u32 value;
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};
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/**
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* struct exynos_srom: platform data for exynos srom controller driver.
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* @dev: platform device pointer
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* @reg_base: srom base address
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* @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
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*/
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struct exynos_srom {
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struct device *dev;
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void __iomem *reg_base;
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struct exynos_srom_reg_dump *reg_offset;
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};
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static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump(
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const unsigned long *rdump,
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unsigned long nr_rdump)
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{
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struct exynos_srom_reg_dump *rd;
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unsigned int i;
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rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
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if (!rd)
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return NULL;
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for (i = 0; i < nr_rdump; ++i)
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rd[i].offset = rdump[i];
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return rd;
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}
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static int exynos_srom_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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struct exynos_srom *srom;
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struct device *dev = &pdev->dev;
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np = dev->of_node;
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if (!np) {
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dev_err(&pdev->dev, "could not find device info\n");
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return -EINVAL;
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}
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srom = devm_kzalloc(&pdev->dev,
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sizeof(struct exynos_srom), GFP_KERNEL);
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if (!srom)
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return -ENOMEM;
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srom->dev = dev;
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srom->reg_base = of_iomap(np, 0);
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if (!srom->reg_base) {
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dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, srom);
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srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
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sizeof(exynos_srom_offsets));
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if (!srom->reg_offset) {
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iounmap(srom->reg_base);
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return -ENOMEM;
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}
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return 0;
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}
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static int exynos_srom_remove(struct platform_device *pdev)
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{
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struct exynos_srom *srom = platform_get_drvdata(pdev);
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kfree(srom->reg_offset);
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iounmap(srom->reg_base);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static void exynos_srom_save(void __iomem *base,
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struct exynos_srom_reg_dump *rd,
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unsigned int num_regs)
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{
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for (; num_regs > 0; --num_regs, ++rd)
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rd->value = readl(base + rd->offset);
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}
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static void exynos_srom_restore(void __iomem *base,
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const struct exynos_srom_reg_dump *rd,
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unsigned int num_regs)
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{
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for (; num_regs > 0; --num_regs, ++rd)
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writel(rd->value, base + rd->offset);
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}
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static int exynos_srom_suspend(struct device *dev)
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{
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struct exynos_srom *srom = dev_get_drvdata(dev);
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exynos_srom_save(srom->reg_base, srom->reg_offset,
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ARRAY_SIZE(exynos_srom_offsets));
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return 0;
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}
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static int exynos_srom_resume(struct device *dev)
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{
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struct exynos_srom *srom = dev_get_drvdata(dev);
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exynos_srom_restore(srom->reg_base, srom->reg_offset,
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ARRAY_SIZE(exynos_srom_offsets));
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return 0;
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}
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#endif
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static const struct of_device_id of_exynos_srom_ids[] = {
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{
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.compatible = "samsung,exynos4210-srom",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, of_exynos_srom_ids);
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static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume);
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static struct platform_driver exynos_srom_driver = {
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.probe = exynos_srom_probe,
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.remove = exynos_srom_remove,
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.driver = {
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.name = "exynos-srom",
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.of_match_table = of_exynos_srom_ids,
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.pm = &exynos_srom_pm_ops,
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},
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};
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module_platform_driver(exynos_srom_driver);
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MODULE_AUTHOR("Pankaj Dubey <pankaj.dubey@samsung.com>");
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MODULE_DESCRIPTION("Exynos SROM Controller Driver");
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MODULE_LICENSE("GPL");
+51
drivers/memory/samsung/exynos-srom.h
+51
drivers/memory/samsung/exynos-srom.h
···
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Exynos SROMC register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS_SROM_H
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#define __EXYNOS_SROM_H __FILE__
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#define EXYNOS_SROMREG(x) (x)
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#define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0)
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#define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4)
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#define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8)
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#define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc)
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#define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10)
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#define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14)
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#define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18)
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/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
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#define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0
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#define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1
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#define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2
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#define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3
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#define EXYNOS_SROM_BW__CS_MASK 0xf
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#define EXYNOS_SROM_BW__NCS0__SHIFT 0
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#define EXYNOS_SROM_BW__NCS1__SHIFT 4
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#define EXYNOS_SROM_BW__NCS2__SHIFT 8
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#define EXYNOS_SROM_BW__NCS3__SHIFT 12
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#define EXYNOS_SROM_BW__NCS4__SHIFT 16
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#define EXYNOS_SROM_BW__NCS5__SHIFT 20
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/* applies to same to BCS0 - BCS3 */
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#define EXYNOS_SROM_BCX__PMC__SHIFT 0
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#define EXYNOS_SROM_BCX__TACP__SHIFT 4
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#define EXYNOS_SROM_BCX__TCAH__SHIFT 8
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#define EXYNOS_SROM_BCX__TCOH__SHIFT 12
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#define EXYNOS_SROM_BCX__TACC__SHIFT 16
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#define EXYNOS_SROM_BCX__TCOS__SHIFT 24
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#define EXYNOS_SROM_BCX__TACS__SHIFT 28
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#endif /* __EXYNOS_SROM_H */