Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: renesas: rzv2h: Use GENMASK for PLL fields

Replace the older FIELD_GET-wrapping helper macros with plain GENMASK
definitions for the PLL CLK1/CLK2 field masks (CPG_PLL_CLK1_KDIV,
CPG_PLL_CLK1_MDIV, CPG_PLL_CLK1_PDIV and CPG_PLL_CLK2_SDIV). Update
rzv2h_cpg_pll_clk_recalc_rate() to explicitly extract those fields with
FIELD_GET and cast the KDIV extraction to s16 to ensure proper sign
extension when computing the PLL output rate.

Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251015192611.241920-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

authored by

Lad Prabhakar and committed by
Geert Uytterhoeven
a8943f7f 36a23904

+8 -7
+8 -7
drivers/clk/renesas/rzv2h-cpg.c
··· 49 49 #define CPG_PLL_STBY_RESETB BIT(0) 50 50 #define CPG_PLL_STBY_RESETB_WEN BIT(16) 51 51 #define CPG_PLL_CLK1(x) ((x) + 0x004) 52 - #define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x))) 53 - #define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x)) 54 - #define CPG_PLL_CLK1_PDIV(x) FIELD_GET(GENMASK(5, 0), (x)) 52 + #define CPG_PLL_CLK1_KDIV GENMASK(31, 16) 53 + #define CPG_PLL_CLK1_MDIV GENMASK(15, 6) 54 + #define CPG_PLL_CLK1_PDIV GENMASK(5, 0) 55 55 #define CPG_PLL_CLK2(x) ((x) + 0x008) 56 - #define CPG_PLL_CLK2_SDIV(x) FIELD_GET(GENMASK(2, 0), (x)) 56 + #define CPG_PLL_CLK2_SDIV GENMASK(2, 0) 57 57 #define CPG_PLL_MON(x) ((x) + 0x010) 58 58 #define CPG_PLL_MON_RESETB BIT(0) 59 59 #define CPG_PLL_MON_LOCK BIT(4) ··· 231 231 clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset)); 232 232 clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset)); 233 233 234 - rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) + 235 - CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2)); 234 + rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) + 235 + (s16)FIELD_GET(CPG_PLL_CLK1_KDIV, clk1), 236 + 16 + FIELD_GET(CPG_PLL_CLK2_SDIV, clk2)); 236 237 237 - return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1)); 238 + return DIV_ROUND_CLOSEST_ULL(rate, FIELD_GET(CPG_PLL_CLK1_PDIV, clk1)); 238 239 } 239 240 240 241 static const struct clk_ops rzv2h_cpg_pll_ops = {