phy: qcom-qmp: Add SM8150 QMP UFS PHY support

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register
defines and support for SM8150 QMP UFS PHY.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

authored by

Vinod Koul and committed by

Kishon Vijay Abraham I 6 years ago a88c85ee 76126f5b

+216

2 changed files

expand all

drivers

phy

qualcomm

phy-qcom-qmp.c

phy-qcom-qmp.h

+120

drivers/phy/qualcomm/phy-qcom-qmp.c

··· 165 165 [QPHY_PCS_READY_STATUS] = 0x160, 166 166 }; 167 167 168 + static const unsigned int sm8150_ufsphy_regs_layout[] = { 169 + [QPHY_START_CTRL] = 0x00, 170 + [QPHY_PCS_READY_STATUS] = 0x180, 171 + }; 172 + 168 173 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { 169 174 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 170 175 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), ··· 884 879 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 885 880 }; 886 881 882 + static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { 883 + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), 884 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 885 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 886 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 887 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 888 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 889 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 890 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 891 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 892 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 893 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 894 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 895 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 896 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 897 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 898 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 899 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 900 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 901 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 902 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 903 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 904 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 905 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 906 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 907 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 908 + 909 + /* Rate B */ 910 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 911 + }; 912 + 913 + static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { 914 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 915 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 916 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 917 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 918 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 919 + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 920 + }; 921 + 922 + static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { 923 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 924 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 925 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 926 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 927 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 928 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 929 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 930 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 931 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 932 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 933 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 934 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 935 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 936 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 937 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 938 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 939 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 940 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 941 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 942 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 943 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 944 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 945 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 946 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 947 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 948 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 949 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 950 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 951 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 952 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 953 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 954 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 955 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 956 + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 957 + 958 + }; 959 + 960 + static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { 961 + QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6d), 962 + QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0a), 963 + QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02), 964 + QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43), 965 + QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1f), 966 + QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xff), 967 + QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02), 968 + }; 887 969 888 970 /* struct qmp_phy_cfg - per-PHY initialization config */ 889 971 struct qmp_phy_cfg { ··· 1366 1274 .pwrdn_ctrl = SW_PWRDN, 1367 1275 1368 1276 .is_dual_lane_phy = true, 1277 + }; 1278 + 1279 + static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 1280 + .type = PHY_TYPE_UFS, 1281 + .nlanes = 2, 1282 + 1283 + .serdes_tbl = sm8150_ufsphy_serdes_tbl, 1284 + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), 1285 + .tx_tbl = sm8150_ufsphy_tx_tbl, 1286 + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), 1287 + .rx_tbl = sm8150_ufsphy_rx_tbl, 1288 + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), 1289 + .pcs_tbl = sm8150_ufsphy_pcs_tbl, 1290 + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), 1291 + .clk_list = sdm845_ufs_phy_clk_l, 1292 + .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), 1293 + .vreg_list = qmp_phy_vreg_l, 1294 + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1295 + .regs = sm8150_ufsphy_regs_layout, 1296 + 1297 + .start_ctrl = SERDES_START, 1298 + .pwrdn_ctrl = SW_PWRDN, 1299 + 1300 + .is_dual_lane_phy = true, 1301 + .no_pcs_sw_reset = true, 1369 1302 }; 1370 1303 1371 1304 static void qcom_qmp_phy_configure(void __iomem *base, ··· 2115 1998 }, { 2116 1999 .compatible = "qcom,msm8998-qmp-usb3-phy", 2117 2000 .data = &msm8998_usb3phy_cfg, 2001 + }, { 2002 + .compatible = "qcom,sm8150-qmp-ufs-phy", 2003 + .data = &sm8150_ufsphy_cfg, 2118 2004 }, 2119 2005 { }, 2120 2006 };

+96

drivers/phy/qualcomm/phy-qcom-qmp.h

··· 313 313 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 314 314 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 315 315 316 + /* Only for QMP V4 PHY - QSERDES COM registers */ 317 + #define QSERDES_V4_COM_PLL_IVCO 0x058 318 + #define QSERDES_V4_COM_CMN_IPTRIM 0x060 319 + #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 320 + #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 321 + #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 322 + #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 323 + #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 324 + #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 325 + #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 326 + #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 327 + #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 328 + #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 329 + #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 330 + #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 331 + #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 332 + #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 333 + #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 334 + #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 335 + #define QSERDES_V4_COM_HSCLK_SEL 0x158 336 + #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 337 + #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 338 + #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 339 + #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 340 + #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 341 + #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 342 + 343 + /* Only for QMP V4 PHY - TX registers */ 344 + #define QSERDES_V4_TX_LANE_MODE_1 0x84 345 + #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 346 + #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 347 + #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 348 + #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 349 + #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 350 + 351 + /* Only for QMP V4 PHY - RX registers */ 352 + #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 353 + #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 354 + #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 355 + #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 356 + #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 357 + #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 358 + #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 359 + #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 360 + #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 361 + #define QSERDES_V4_RX_RX_TERM_BW 0x080 362 + #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 363 + #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 364 + #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 365 + #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 366 + #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 367 + #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 368 + #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 369 + #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 370 + #define QSERDES_V4_RX_SIGDET_LVL 0x120 371 + #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 372 + #define QSERDES_V4_RX_RX_BAND 0x128 373 + #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 374 + #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 375 + #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 376 + #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 377 + #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 378 + #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 379 + #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 380 + #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 381 + #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 382 + #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 383 + #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 384 + #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 385 + #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 386 + #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 387 + #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 388 + #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 389 + 390 + /* Only for QMP V4 PHY - PCS registers */ 391 + #define QPHY_V4_PHY_START 0x000 392 + #define QPHY_V4_POWER_DOWN_CONTROL 0x004 393 + #define QPHY_V4_SW_RESET 0x008 394 + #define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00c 395 + #define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010 396 + #define QPHY_V4_PLL_CNTL 0x02c 397 + #define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030 398 + #define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038 399 + #define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060 400 + #define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074 401 + #define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0b4 402 + #define QPHY_V4_DEBUG_BUS_CLKSEL 0x124 403 + #define QPHY_V4_LINECFG_DISABLE 0x148 404 + #define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150 405 + #define QPHY_V4_RX_SIGDET_CTRL2 0x158 406 + #define QPHY_V4_TX_PWM_GEAR_BAND 0x160 407 + #define QPHY_V4_TX_HS_GEAR_BAND 0x168 408 + #define QPHY_V4_PCS_READY_STATUS 0x180 409 + #define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8 410 + #define QPHY_V4_MULTI_LANE_CTRL1 0x1e0 411 + 316 412 #endif