xtensa: enforce slab alignment to maximum register width

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.

Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now. But the S6000 variant will raise this to 16.

Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

authored by

Oskar Schirmer and committed by

Chris Zankel 17 years ago a81cbd2d c947a585

1 changed file

expand all

arch

xtensa

include

asm

processor.h

arch/xtensa/include/asm/processor.h

··· 25 25 # error Linux requires the Xtensa Windowed Registers Option. 26 26 #endif 27 27 28 + #define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH 29 + 28 30 /* 29 31 * User space process size: 1 GB. 30 32 * Windowed call ABI requires caller and callee to be located within the same