dt-bindings: phy: Clarify ULPI PHY source clock

cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group.
PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the
DAP_MCLK2 pad.

Signed-off-by: Marcel Ziswiler <[e-mail]>
Reviewed-by: Dmitry Osipenko <[e-mail]>
Reviewed-by: Rob Herring <[e-mail]>
Signed-off-by: Thierry Reding <[e-mail]>

Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt

···
    - timer: The timeout clock (clk_m). Present if phy_type == utmi.
    - utmi-pads: The clock needed to access the UTMI pad control registers.
      Present if phy_type == utmi.
-   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+   - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
+     with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
+     "nvidia,function" pllp_out4).
      Present if phy_type == ulpi, and ULPI link mode is in use.
  - resets : Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.