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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/xe/irq: Convert register access to use xe_mmio
Stop using GT pointers for register access. This misusage has been
especially confusing in interrupt code because even though some of the
interrupts are related to GTs (or engines within GTs), the interrupt
registers themselves live outside the GT, in the sgunit.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-55-matthew.d.roper@intel.com
+32
-31
+32
-31
drivers/gpu/drm/xe/xe_irq.c
+32
-31
drivers/gpu/drm/xe/xe_irq.c
···
30
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#define IIR(offset) XE_REG(offset + 0x8)
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#define IER(offset) XE_REG(offset + 0xc)
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-
static void assert_iir_is_zero(struct xe_gt *mmio, struct xe_reg reg)
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+
static void assert_iir_is_zero(struct xe_mmio *mmio, struct xe_reg reg)
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{
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u32 val = xe_mmio_read32(mmio, reg);
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if (val == 0)
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return;
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-
drm_WARN(>_to_xe(mmio)->drm, 1,
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+
drm_WARN(&mmio->tile->xe->drm, 1,
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"Interrupt register 0x%x is not zero: 0x%08x\n",
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reg.addr, val);
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xe_mmio_write32(mmio, reg, 0xffffffff);
···
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*/
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static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits)
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{
55
-
struct xe_gt *mmio = tile->primary_gt;
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+
struct xe_mmio *mmio = &tile->mmio;
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/*
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* If we're just enabling an interrupt now, it shouldn't already
···
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/* Mask and disable all interrupts. */
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static void mask_and_disable(struct xe_tile *tile, u32 irqregs)
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{
73
-
struct xe_gt *mmio = tile->primary_gt;
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+
struct xe_mmio *mmio = &tile->mmio;
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xe_mmio_write32(mmio, IMR(irqregs), ~0);
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/* Posting read */
···
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static u32 xelp_intr_disable(struct xe_device *xe)
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{
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-
struct xe_gt *mmio = xe_root_mmio_gt(xe);
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+
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
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xe_mmio_write32(mmio, GFX_MSTR_IRQ, 0);
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93
···
103
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static u32
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gu_misc_irq_ack(struct xe_device *xe, const u32 master_ctl)
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{
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-
struct xe_gt *mmio = xe_root_mmio_gt(xe);
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+
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
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u32 iir;
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if (!(master_ctl & GU_MISC_IRQ))
···
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static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
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{
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-
struct xe_gt *mmio = xe_root_mmio_gt(xe);
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+
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
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xe_mmio_write32(mmio, GFX_MSTR_IRQ, MASTER_IRQ);
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if (stall)
···
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void xe_irq_enable_hwe(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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+
struct xe_mmio *mmio = >->mmio;
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u32 ccs_mask, bcs_mask;
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u32 irqs, dmask, smask;
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u32 gsc_mask = 0;
···
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if (!xe_gt_is_media_type(gt)) {
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/* Enable interrupts for each engine class */
159
-
xe_mmio_write32(gt, RENDER_COPY_INTR_ENABLE, dmask);
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+
xe_mmio_write32(mmio, RENDER_COPY_INTR_ENABLE, dmask);
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159
if (ccs_mask)
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-
xe_mmio_write32(gt, CCS_RSVD_INTR_ENABLE, smask);
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+
xe_mmio_write32(mmio, CCS_RSVD_INTR_ENABLE, smask);
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/* Unmask interrupts for each engine instance */
164
-
xe_mmio_write32(gt, RCS0_RSVD_INTR_MASK, ~smask);
165
-
xe_mmio_write32(gt, BCS_RSVD_INTR_MASK, ~smask);
163
+
xe_mmio_write32(mmio, RCS0_RSVD_INTR_MASK, ~smask);
164
+
xe_mmio_write32(mmio, BCS_RSVD_INTR_MASK, ~smask);
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if (bcs_mask & (BIT(1)|BIT(2)))
167
-
xe_mmio_write32(gt, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
166
+
xe_mmio_write32(mmio, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
168
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if (bcs_mask & (BIT(3)|BIT(4)))
169
-
xe_mmio_write32(gt, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
168
+
xe_mmio_write32(mmio, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
170
169
if (bcs_mask & (BIT(5)|BIT(6)))
171
-
xe_mmio_write32(gt, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
170
+
xe_mmio_write32(mmio, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
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171
if (bcs_mask & (BIT(7)|BIT(8)))
173
-
xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
172
+
xe_mmio_write32(mmio, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
174
173
if (ccs_mask & (BIT(0)|BIT(1)))
175
-
xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK, ~dmask);
174
+
xe_mmio_write32(mmio, CCS0_CCS1_INTR_MASK, ~dmask);
176
175
if (ccs_mask & (BIT(2)|BIT(3)))
177
-
xe_mmio_write32(gt, CCS2_CCS3_INTR_MASK, ~dmask);
176
+
xe_mmio_write32(mmio, CCS2_CCS3_INTR_MASK, ~dmask);
178
177
}
179
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180
179
if (xe_gt_is_media_type(gt) || MEDIA_VER(xe) < 13) {
181
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/* Enable interrupts for each engine class */
182
-
xe_mmio_write32(gt, VCS_VECS_INTR_ENABLE, dmask);
181
+
xe_mmio_write32(mmio, VCS_VECS_INTR_ENABLE, dmask);
183
182
184
183
/* Unmask interrupts for each engine instance */
185
-
xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK, ~dmask);
186
-
xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK, ~dmask);
187
-
xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK, ~dmask);
184
+
xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask);
185
+
xe_mmio_write32(mmio, VCS2_VCS3_INTR_MASK, ~dmask);
186
+
xe_mmio_write32(mmio, VECS0_VECS1_INTR_MASK, ~dmask);
188
187
189
188
/*
190
189
* the heci2 interrupt is enabled via the same register as the
···
198
197
}
199
198
200
199
if (gsc_mask) {
201
-
xe_mmio_write32(gt, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);
202
-
xe_mmio_write32(gt, GUNIT_GSC_INTR_MASK, ~gsc_mask);
200
+
xe_mmio_write32(mmio, GUNIT_GSC_INTR_ENABLE, gsc_mask | heci_mask);
201
+
xe_mmio_write32(mmio, GUNIT_GSC_INTR_MASK, ~gsc_mask);
203
202
}
204
203
if (heci_mask)
205
-
xe_mmio_write32(gt, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));
204
+
xe_mmio_write32(mmio, HECI2_RSVD_INTR_MASK, ~(heci_mask << 16));
206
205
}
207
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}
208
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static u32
210
209
gt_engine_identity(struct xe_device *xe,
211
-
struct xe_gt *mmio,
210
+
struct xe_mmio *mmio,
212
211
const unsigned int bank,
213
212
const unsigned int bit)
214
213
{
···
292
291
u32 *identity)
293
292
{
294
293
struct xe_device *xe = tile_to_xe(tile);
295
-
struct xe_gt *mmio = tile->primary_gt;
294
+
struct xe_mmio *mmio = &tile->mmio;
296
295
unsigned int bank, bit;
297
296
u16 instance, intr_vec;
298
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enum xe_engine_class class;
···
377
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378
377
static u32 dg1_intr_disable(struct xe_device *xe)
379
378
{
380
-
struct xe_gt *mmio = xe_root_mmio_gt(xe);
379
+
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
381
380
u32 val;
382
381
383
382
/* First disable interrupts */
···
395
394
396
395
static void dg1_intr_enable(struct xe_device *xe, bool stall)
397
396
{
398
-
struct xe_gt *mmio = xe_root_mmio_gt(xe);
397
+
struct xe_mmio *mmio = xe_root_tile_mmio(xe);
399
398
400
399
xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ);
401
400
if (stall)
···
432
431
}
433
432
434
433
for_each_tile(tile, xe, id) {
435
-
struct xe_gt *mmio = tile->primary_gt;
434
+
struct xe_mmio *mmio = &tile->mmio;
436
435
437
436
if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0)
438
437
continue;
···
475
474
476
475
static void gt_irq_reset(struct xe_tile *tile)
477
476
{
478
-
struct xe_gt *mmio = tile->primary_gt;
477
+
struct xe_mmio *mmio = &tile->mmio;
479
478
480
479
u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt,
481
480
XE_ENGINE_CLASS_COMPUTE);
···
548
547
549
548
static void dg1_irq_reset_mstr(struct xe_tile *tile)
550
549
{
551
-
struct xe_gt *mmio = tile->primary_gt;
550
+
struct xe_mmio *mmio = &tile->mmio;
552
551
553
552
xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);
554
553
}