cxl/port: Fix cxl_test register enumeration regression

The cxl_test unit test environment models a CXL topology for
sysfs/user-ABI regression testing. It uses interface mocking via the
"--wrap=" linker option to redirect cxl_core routines that parse
hardware registers with versions that just publish objects, like
devm_cxl_enumerate_decoders().

Starting with:

Commit 19ab69a60e3b ("cxl/port: Store the port's Component Register mappings in struct cxl_port")

...port register enumeration is moved into devm_cxl_add_port(). This
conflicts with the "cxl_test avoids emulating registers stance" so
either the port code needs to be refactored (too violent), or modified
so that register enumeration is skipped on "fake" cxl_test ports
(annoying, but straightforward).

This conflict has happened previously and the "check for platform
device" workaround to avoid instrusive refactoring was deployed in those
scenarios. In general, refactoring should only benefit production code,
test code needs to remain minimally instrusive to the greatest extent
possible.

This was missed previously because it may sometimes just cause warning
messages to be emitted, but it can also cause test failures. The
backport to -stable is only nice to have for clean cxl_test runs.

Fixes: 19ab69a60e3b ("cxl/port: Store the port's Component Register mappings in struct cxl_port")
Cc: stable@vger.kernel.org
Reported-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/169476525052.1013896.6235102957693675187.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

Changed files
+9 -4
drivers
cxl
core
+9 -4
drivers/cxl/core/port.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3 + #include <linux/platform_device.h> 3 4 #include <linux/memregion.h> 4 5 #include <linux/workqueue.h> 5 6 #include <linux/debugfs.h> ··· 707 706 return cxl_setup_regs(map); 708 707 } 709 708 710 - static inline int cxl_port_setup_regs(struct cxl_port *port, 711 - resource_size_t component_reg_phys) 709 + static int cxl_port_setup_regs(struct cxl_port *port, 710 + resource_size_t component_reg_phys) 712 711 { 712 + if (dev_is_platform(port->uport_dev)) 713 + return 0; 713 714 return cxl_setup_comp_regs(&port->dev, &port->comp_map, 714 715 component_reg_phys); 715 716 } 716 717 717 - static inline int cxl_dport_setup_regs(struct cxl_dport *dport, 718 - resource_size_t component_reg_phys) 718 + static int cxl_dport_setup_regs(struct cxl_dport *dport, 719 + resource_size_t component_reg_phys) 719 720 { 721 + if (dev_is_platform(dport->dport_dev)) 722 + return 0; 720 723 return cxl_setup_comp_regs(dport->dport_dev, &dport->comp_map, 721 724 component_reg_phys); 722 725 }