Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge patch series "Eight small UFS patches"

Bart Van Assche <bvanassche@acm.org> says:

Hi Martin,

This patch series includes two bug fixes for this development cycle
and six small patches that are intended for the next merge window. If
applying the first two patches only during the current development
cycle would be inconvenient, postponing all patches until the next
merge window is fine with me.

Please consider including these patches in the upstream kernel.

Thanks,

Bart.

[mkp: Applied patches #1 and #2 to 6.18/scsi-fixes]

Link: https://patch.msgid.link/20251014200118.3390839-1-bvanassche@acm.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

+12 -13
+2 -4
drivers/ufs/core/ufs-mcq.c
··· 568 568 569 569 id = hwq->id; 570 570 571 - mutex_lock(&hwq->sq_mutex); 571 + guard(mutex)(&hwq->sq_mutex); 572 572 573 573 /* stop the SQ fetching before working on it */ 574 574 err = ufshcd_mcq_sq_stop(hba, hwq); 575 575 if (err) 576 - goto unlock; 576 + return err; 577 577 578 578 /* SQCTI = EXT_IID, IID, LUN, Task Tag */ 579 579 nexus = lrbp->lun << 8 | task_tag; ··· 600 600 if (ufshcd_mcq_sq_start(hba, hwq)) 601 601 err = -ETIMEDOUT; 602 602 603 - unlock: 604 - mutex_unlock(&hwq->sq_mutex); 605 603 return err; 606 604 } 607 605
-1
drivers/ufs/core/ufs_trace.h
··· 42 42 #define UFS_CMD_TRACE_STRINGS \ 43 43 EM(UFS_CMD_SEND, "send_req") \ 44 44 EM(UFS_CMD_COMP, "complete_rsp") \ 45 - EM(UFS_DEV_COMP, "dev_complete") \ 46 45 EM(UFS_QUERY_SEND, "query_send") \ 47 46 EM(UFS_QUERY_COMP, "query_complete") \ 48 47 EM(UFS_QUERY_ERR, "query_complete_err") \
-1
drivers/ufs/core/ufs_trace_types.h
··· 5 5 enum ufs_trace_str_t { 6 6 UFS_CMD_SEND, 7 7 UFS_CMD_COMP, 8 - UFS_DEV_COMP, 9 8 UFS_QUERY_SEND, 10 9 UFS_QUERY_COMP, 11 10 UFS_QUERY_ERR,
+2
drivers/ufs/core/ufshcd-priv.h
··· 6 6 #include <linux/pm_runtime.h> 7 7 #include <ufs/ufshcd.h> 8 8 9 + void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs); 10 + 9 11 static inline bool ufshcd_is_user_access_allowed(struct ufs_hba *hba) 10 12 { 11 13 return !hba->shutting_down;
+4 -5
drivers/ufs/core/ufshcd.c
··· 2619 2619 2620 2620 init_completion(&uic_cmd->done); 2621 2621 2622 - uic_cmd->cmd_active = 1; 2622 + uic_cmd->cmd_active = true; 2623 2623 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2624 2624 2625 2625 return 0; ··· 5582 5582 guard(spinlock_irqsave)(hba->host->host_lock); 5583 5583 cmd = hba->active_uic_cmd; 5584 5584 if (!cmd) 5585 - goto unlock; 5585 + return retval; 5586 5586 5587 5587 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5588 5588 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); ··· 5591 5591 cmd->argument2 |= ufshcd_get_uic_cmd_result(hba); 5592 5592 cmd->argument3 = ufshcd_get_dme_attr_val(hba); 5593 5593 if (!hba->uic_async_done) 5594 - cmd->cmd_active = 0; 5594 + cmd->cmd_active = false; 5595 5595 complete(&cmd->done); 5596 5596 retval = IRQ_HANDLED; 5597 5597 } 5598 5598 5599 5599 if (intr_status & UFSHCD_UIC_PWR_MASK && hba->uic_async_done) { 5600 - cmd->cmd_active = 0; 5600 + cmd->cmd_active = false; 5601 5601 complete(hba->uic_async_done); 5602 5602 retval = IRQ_HANDLED; 5603 5603 } ··· 5605 5605 if (retval == IRQ_HANDLED) 5606 5606 ufshcd_add_uic_command_trace(hba, cmd, UFS_CMD_COMP); 5607 5607 5608 - unlock: 5609 5608 return retval; 5610 5609 } 5611 5610
+1 -2
include/ufs/ufshcd.h
··· 78 78 const u32 argument1; 79 79 u32 argument2; 80 80 u32 argument3; 81 - int cmd_active; 81 + bool cmd_active; 82 82 struct completion done; 83 83 }; 84 84 ··· 1297 1297 1298 1298 void ufshcd_enable_irq(struct ufs_hba *hba); 1299 1299 void ufshcd_disable_irq(struct ufs_hba *hba); 1300 - void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs); 1301 1300 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1302 1301 int ufshcd_hba_enable(struct ufs_hba *hba); 1303 1302 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
+3
include/ufs/ufshci.h
··· 83 83 }; 84 84 85 85 enum { 86 + /* Submission Queue (SQ) Configuration Registers */ 86 87 REG_SQATTR = 0x0, 87 88 REG_SQLBA = 0x4, 88 89 REG_SQUBA = 0x8, 89 90 REG_SQDAO = 0xC, 90 91 REG_SQISAO = 0x10, 91 92 93 + /* Completion Queue (CQ) Configuration Registers */ 92 94 REG_CQATTR = 0x20, 93 95 REG_CQLBA = 0x24, 94 96 REG_CQUBA = 0x28, ··· 98 96 REG_CQISAO = 0x30, 99 97 }; 100 98 99 + /* Operation and Runtime Registers - Submission Queues and Completion Queues */ 101 100 enum { 102 101 REG_SQHP = 0x0, 103 102 REG_SQTP = 0x4,