···991010All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.1111For a description of the MMSYS_CONFIG binding, see1212-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.1212+Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.13131414DISP function blocks1515====================
···2020 - snps,dwcmshc-sdhci21212222 reg:2323- minItems: 12424- items:2525- - description: Offset and length of the register set for the device2323+ maxItems: 126242725 interrupts:2826 maxItems: 1
···11+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause22+%YAML 1.233+---44+$id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#55+$schema: http://devicetree.org/meta-schemas/core.yaml#66+77+title: Samsung SoC series UFS host controller Device Tree Bindings88+99+maintainers:1010+ - Alim Akhtar <alim.akhtar@samsung.com>1111+1212+description: |1313+ Each Samsung UFS host controller instance should have its own node.1414+ This binding define Samsung specific binding other then what is used1515+ in the common ufshcd bindings1616+ [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt1717+1818+properties:1919+2020+ compatible:2121+ enum:2222+ - samsung,exynos7-ufs2323+2424+ reg:2525+ items:2626+ - description: HCI register2727+ - description: vendor specific register2828+ - description: unipro register2929+ - description: UFS protector register3030+3131+ reg-names:3232+ items:3333+ - const: hci3434+ - const: vs_hci3535+ - const: unipro3636+ - const: ufsp3737+3838+ clocks:3939+ items:4040+ - description: ufs link core clock4141+ - description: unipro main clock4242+4343+ clock-names:4444+ items:4545+ - const: core_clk4646+ - const: sclk_unipro_main4747+4848+ interrupts:4949+ maxItems: 15050+5151+ phys:5252+ maxItems: 15353+5454+ phy-names:5555+ const: ufs-phy5656+5757+required:5858+ - compatible5959+ - reg6060+ - interrupts6161+ - phys6262+ - phy-names6363+ - clocks6464+ - clock-names6565+6666+additionalProperties: false6767+6868+examples:6969+ - |7070+ #include <dt-bindings/interrupt-controller/arm-gic.h>7171+ #include <dt-bindings/clock/exynos7-clk.h>7272+7373+ ufs: ufs@15570000 {7474+ compatible = "samsung,exynos7-ufs";7575+ reg = <0x15570000 0x100>,7676+ <0x15570100 0x100>,7777+ <0x15571000 0x200>,7878+ <0x15572000 0x300>;7979+ reg-names = "hci", "vs_hci", "unipro", "ufsp";8080+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;8181+ clocks = <&clock_fsys1 ACLK_UFS20_LINK>,8282+ <&clock_fsys1 SCLK_UFSUNIPRO20_USER>;8383+ clock-names = "core_clk", "sclk_unipro_main";8484+ pinctrl-names = "default";8585+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;8686+ phys = <&ufs_phy>;8787+ phy-names = "ufs-phy";8888+ };8989+...
+1-1
Documentation/networking/dsa/sja1105.rst
···296296Device Tree bindings and board design297297=====================================298298299299-This section references ``Documentation/devicetree/bindings/net/dsa/sja1105.txt``299299+This section references ``Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml``300300and aims to showcase some potential switch caveats.301301302302RMII PHY role and out-of-band signaling
+5-1
drivers/of/device.c
···8585 break;8686 }87878888- if (i != count && of_reserved_mem_device_init_by_idx(dev, of_node, i))8888+ /*8989+ * Attempt to initialize a restricted-dma-pool region if one was found.9090+ * Note that count can hold a negative error code.9191+ */9292+ if (i < count && of_reserved_mem_device_init_by_idx(dev, of_node, i))8993 dev_warn(dev, "failed to initialise \"restricted-dma-pool\" memory node\n");9094}9195