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ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUs

Avoid the errata 430973 workaround for non-Cortex A8 CPUs. Having this
workaround enabled introduces an additional branch target buffer flush
into the context switching path, something we wish to avoid. To allow
this errata to be enabled in multiplatform kernels while reducing its
impact, rearrange the Cortex-A8 CPU support to avoid impacting on other
Version 7 CPUs.

Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Russell King a6d74678 e5a5de44

+36 -4
+8 -4
arch/arm/mm/proc-v7-2level.S
··· 37 37 * It is assumed that: 38 38 * - we are not using split page tables 39 39 */ 40 - ENTRY(cpu_v7_switch_mm) 40 + ENTRY(cpu_ca8_switch_mm) 41 41 #ifdef CONFIG_MMU 42 42 mov r2, #0 43 - mmid r1, r1 @ get mm->context.id 44 - ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 45 - ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 46 43 #ifdef CONFIG_ARM_ERRATA_430973 47 44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 48 45 #endif 46 + #endif 47 + ENTRY(cpu_v7_switch_mm) 48 + #ifdef CONFIG_MMU 49 + mmid r1, r1 @ get mm->context.id 50 + ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 51 + ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 49 52 #ifdef CONFIG_PID_IN_CONTEXTIDR 50 53 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 51 54 lsr r2, r2, #8 @ extract the PID ··· 64 61 #endif 65 62 bx lr 66 63 ENDPROC(cpu_v7_switch_mm) 64 + ENDPROC(cpu_ca8_switch_mm) 67 65 68 66 /* 69 67 * cpu_v7_set_pte_ext(ptep, pte)
+28
arch/arm/mm/proc-v7.S
··· 153 153 #endif 154 154 155 155 /* 156 + * Cortex-A8 157 + */ 158 + globl_equ cpu_ca8_proc_init, cpu_v7_proc_init 159 + globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin 160 + globl_equ cpu_ca8_reset, cpu_v7_reset 161 + globl_equ cpu_ca8_do_idle, cpu_v7_do_idle 162 + globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area 163 + globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext 164 + globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size 165 + #ifdef CONFIG_ARM_CPU_SUSPEND 166 + globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend 167 + globl_equ cpu_ca8_do_resume, cpu_v7_do_resume 168 + #endif 169 + 170 + /* 156 171 * Cortex-A9 processor functions 157 172 */ 158 173 globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init ··· 466 451 467 452 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 468 453 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 454 + #ifndef CONFIG_ARM_LPAE 455 + define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 469 456 define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 457 + #endif 470 458 #ifdef CONFIG_CPU_PJ4B 471 459 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 472 460 #endif ··· 524 506 .long 0xff0ffff0 525 507 __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions 526 508 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 509 + 510 + /* 511 + * ARM Ltd. Cortex A8 processor. 512 + */ 513 + .type __v7_ca8_proc_info, #object 514 + __v7_ca8_proc_info: 515 + .long 0x410fc080 516 + .long 0xff0ffff0 517 + __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions 518 + .size __v7_ca8_proc_info, . - __v7_ca8_proc_info 527 519 528 520 #endif /* CONFIG_ARM_LPAE */ 529 521