tjh.dev / kernel
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kernel os linux
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clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents

Use ARRAY_SIZE for num_parents instead of hardcoding the value.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-7-ansuelsmth@gmail.com

authored by

Ansuel Smith and committed by
Bjorn Andersson a6aedd65 cb02866f

+34 -34
+34 -34
drivers/clk/qcom/gcc-ipq806x.c
··· 373 373 .hw.init = &(struct clk_init_data){ 374 374 .name = "gsbi1_uart_src", 375 375 .parent_data = gcc_pxo_pll8, 376 - .num_parents = 2, 376 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 377 377 .ops = &clk_rcg_ops, 378 378 .flags = CLK_SET_PARENT_GATE, 379 379 }, ··· 424 424 .hw.init = &(struct clk_init_data){ 425 425 .name = "gsbi2_uart_src", 426 426 .parent_data = gcc_pxo_pll8, 427 - .num_parents = 2, 427 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 428 428 .ops = &clk_rcg_ops, 429 429 .flags = CLK_SET_PARENT_GATE, 430 430 }, ··· 475 475 .hw.init = &(struct clk_init_data){ 476 476 .name = "gsbi4_uart_src", 477 477 .parent_data = gcc_pxo_pll8, 478 - .num_parents = 2, 478 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 479 479 .ops = &clk_rcg_ops, 480 480 .flags = CLK_SET_PARENT_GATE, 481 481 }, ··· 526 526 .hw.init = &(struct clk_init_data){ 527 527 .name = "gsbi5_uart_src", 528 528 .parent_data = gcc_pxo_pll8, 529 - .num_parents = 2, 529 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 530 530 .ops = &clk_rcg_ops, 531 531 .flags = CLK_SET_PARENT_GATE, 532 532 }, ··· 577 577 .hw.init = &(struct clk_init_data){ 578 578 .name = "gsbi6_uart_src", 579 579 .parent_data = gcc_pxo_pll8, 580 - .num_parents = 2, 580 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 581 581 .ops = &clk_rcg_ops, 582 582 .flags = CLK_SET_PARENT_GATE, 583 583 }, ··· 628 628 .hw.init = &(struct clk_init_data){ 629 629 .name = "gsbi7_uart_src", 630 630 .parent_data = gcc_pxo_pll8, 631 - .num_parents = 2, 631 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 632 632 .ops = &clk_rcg_ops, 633 633 .flags = CLK_SET_PARENT_GATE, 634 634 }, ··· 692 692 .hw.init = &(struct clk_init_data){ 693 693 .name = "gsbi1_qup_src", 694 694 .parent_data = gcc_pxo_pll8, 695 - .num_parents = 2, 695 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 696 696 .ops = &clk_rcg_ops, 697 697 .flags = CLK_SET_PARENT_GATE, 698 698 }, ··· 743 743 .hw.init = &(struct clk_init_data){ 744 744 .name = "gsbi2_qup_src", 745 745 .parent_data = gcc_pxo_pll8, 746 - .num_parents = 2, 746 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 747 747 .ops = &clk_rcg_ops, 748 748 .flags = CLK_SET_PARENT_GATE, 749 749 }, ··· 794 794 .hw.init = &(struct clk_init_data){ 795 795 .name = "gsbi4_qup_src", 796 796 .parent_data = gcc_pxo_pll8, 797 - .num_parents = 2, 797 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 798 798 .ops = &clk_rcg_ops, 799 799 .flags = CLK_SET_PARENT_GATE, 800 800 }, ··· 845 845 .hw.init = &(struct clk_init_data){ 846 846 .name = "gsbi5_qup_src", 847 847 .parent_data = gcc_pxo_pll8, 848 - .num_parents = 2, 848 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 849 849 .ops = &clk_rcg_ops, 850 850 .flags = CLK_SET_PARENT_GATE, 851 851 }, ··· 896 896 .hw.init = &(struct clk_init_data){ 897 897 .name = "gsbi6_qup_src", 898 898 .parent_data = gcc_pxo_pll8, 899 - .num_parents = 2, 899 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 900 900 .ops = &clk_rcg_ops, 901 901 .flags = CLK_SET_PARENT_GATE, 902 902 }, ··· 947 947 .hw.init = &(struct clk_init_data){ 948 948 .name = "gsbi7_qup_src", 949 949 .parent_data = gcc_pxo_pll8, 950 - .num_parents = 2, 950 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 951 951 .ops = &clk_rcg_ops, 952 952 .flags = CLK_SET_PARENT_GATE, 953 953 }, ··· 1099 1099 .hw.init = &(struct clk_init_data){ 1100 1100 .name = "gp0_src", 1101 1101 .parent_data = gcc_pxo_pll8_cxo, 1102 - .num_parents = 3, 1102 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1103 1103 .ops = &clk_rcg_ops, 1104 1104 .flags = CLK_SET_PARENT_GATE, 1105 1105 }, ··· 1150 1150 .hw.init = &(struct clk_init_data){ 1151 1151 .name = "gp1_src", 1152 1152 .parent_data = gcc_pxo_pll8_cxo, 1153 - .num_parents = 3, 1153 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1154 1154 .ops = &clk_rcg_ops, 1155 1155 .flags = CLK_SET_RATE_GATE, 1156 1156 }, ··· 1201 1201 .hw.init = &(struct clk_init_data){ 1202 1202 .name = "gp2_src", 1203 1203 .parent_data = gcc_pxo_pll8_cxo, 1204 - .num_parents = 3, 1204 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo), 1205 1205 .ops = &clk_rcg_ops, 1206 1206 .flags = CLK_SET_RATE_GATE, 1207 1207 }, ··· 1257 1257 .hw.init = &(struct clk_init_data){ 1258 1258 .name = "prng_src", 1259 1259 .parent_data = gcc_pxo_pll8, 1260 - .num_parents = 2, 1260 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1261 1261 .ops = &clk_rcg_ops, 1262 1262 }, 1263 1263 }, ··· 1321 1321 .hw.init = &(struct clk_init_data){ 1322 1322 .name = "sdc1_src", 1323 1323 .parent_data = gcc_pxo_pll8, 1324 - .num_parents = 2, 1324 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1325 1325 .ops = &clk_rcg_ops, 1326 1326 }, 1327 1327 } ··· 1371 1371 .hw.init = &(struct clk_init_data){ 1372 1372 .name = "sdc3_src", 1373 1373 .parent_data = gcc_pxo_pll8, 1374 - .num_parents = 2, 1374 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1375 1375 .ops = &clk_rcg_ops, 1376 1376 }, 1377 1377 } ··· 1456 1456 .hw.init = &(struct clk_init_data){ 1457 1457 .name = "tsif_ref_src", 1458 1458 .parent_data = gcc_pxo_pll8, 1459 - .num_parents = 2, 1459 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8), 1460 1460 .ops = &clk_rcg_ops, 1461 1461 }, 1462 1462 } ··· 1620 1620 .hw.init = &(struct clk_init_data){ 1621 1621 .name = "pcie_ref_src", 1622 1622 .parent_data = gcc_pxo_pll3, 1623 - .num_parents = 2, 1623 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1624 1624 .ops = &clk_rcg_ops, 1625 1625 .flags = CLK_SET_RATE_GATE, 1626 1626 }, ··· 1714 1714 .hw.init = &(struct clk_init_data){ 1715 1715 .name = "pcie1_ref_src", 1716 1716 .parent_data = gcc_pxo_pll3, 1717 - .num_parents = 2, 1717 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1718 1718 .ops = &clk_rcg_ops, 1719 1719 .flags = CLK_SET_RATE_GATE, 1720 1720 }, ··· 1808 1808 .hw.init = &(struct clk_init_data){ 1809 1809 .name = "pcie2_ref_src", 1810 1810 .parent_data = gcc_pxo_pll3, 1811 - .num_parents = 2, 1811 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1812 1812 .ops = &clk_rcg_ops, 1813 1813 .flags = CLK_SET_RATE_GATE, 1814 1814 }, ··· 1907 1907 .hw.init = &(struct clk_init_data){ 1908 1908 .name = "sata_ref_src", 1909 1909 .parent_data = gcc_pxo_pll3, 1910 - .num_parents = 2, 1910 + .num_parents = ARRAY_SIZE(gcc_pxo_pll3), 1911 1911 .ops = &clk_rcg_ops, 1912 1912 .flags = CLK_SET_RATE_GATE, 1913 1913 }, ··· 2048 2048 .hw.init = &(struct clk_init_data){ 2049 2049 .name = "usb30_master_ref_src", 2050 2050 .parent_data = gcc_pxo_pll8_pll0, 2051 - .num_parents = 3, 2051 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2052 2052 .ops = &clk_rcg_ops, 2053 2053 .flags = CLK_SET_RATE_GATE, 2054 2054 }, ··· 2122 2122 .hw.init = &(struct clk_init_data){ 2123 2123 .name = "usb30_utmi_clk", 2124 2124 .parent_data = gcc_pxo_pll8_pll0, 2125 - .num_parents = 3, 2125 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2126 2126 .ops = &clk_rcg_ops, 2127 2127 .flags = CLK_SET_RATE_GATE, 2128 2128 }, ··· 2196 2196 .hw.init = &(struct clk_init_data){ 2197 2197 .name = "usb_hs1_xcvr_src", 2198 2198 .parent_data = gcc_pxo_pll8_pll0, 2199 - .num_parents = 3, 2199 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2200 2200 .ops = &clk_rcg_ops, 2201 2201 .flags = CLK_SET_RATE_GATE, 2202 2202 }, ··· 2262 2262 .hw.init = &(struct clk_init_data){ 2263 2263 .name = "usb_fs1_xcvr_src", 2264 2264 .parent_data = gcc_pxo_pll8_pll0, 2265 - .num_parents = 3, 2265 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0), 2266 2266 .ops = &clk_rcg_ops, 2267 2267 .flags = CLK_SET_RATE_GATE, 2268 2268 }, ··· 2398 2398 .hw.init = &(struct clk_init_data){ 2399 2399 .name = "gmac_core1_src", 2400 2400 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2401 - .num_parents = 5, 2401 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2402 2402 .ops = &clk_dyn_rcg_ops, 2403 2403 }, 2404 2404 }, ··· 2470 2470 .hw.init = &(struct clk_init_data){ 2471 2471 .name = "gmac_core2_src", 2472 2472 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2473 - .num_parents = 5, 2473 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2474 2474 .ops = &clk_dyn_rcg_ops, 2475 2475 }, 2476 2476 }, ··· 2542 2542 .hw.init = &(struct clk_init_data){ 2543 2543 .name = "gmac_core3_src", 2544 2544 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2545 - .num_parents = 5, 2545 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2546 2546 .ops = &clk_dyn_rcg_ops, 2547 2547 }, 2548 2548 }, ··· 2614 2614 .hw.init = &(struct clk_init_data){ 2615 2615 .name = "gmac_core4_src", 2616 2616 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2617 - .num_parents = 5, 2617 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2618 2618 .ops = &clk_dyn_rcg_ops, 2619 2619 }, 2620 2620 }, ··· 2674 2674 .hw.init = &(struct clk_init_data){ 2675 2675 .name = "nss_tcm_src", 2676 2676 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2677 - .num_parents = 5, 2677 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2678 2678 .ops = &clk_dyn_rcg_ops, 2679 2679 }, 2680 2680 }, ··· 2752 2752 .hw.init = &(struct clk_init_data){ 2753 2753 .name = "ubi32_core1_src_clk", 2754 2754 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2755 - .num_parents = 5, 2755 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2756 2756 .ops = &clk_dyn_rcg_ops, 2757 2757 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2758 2758 }, ··· 2805 2805 .hw.init = &(struct clk_init_data){ 2806 2806 .name = "ubi32_core2_src_clk", 2807 2807 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0, 2808 - .num_parents = 5, 2808 + .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0), 2809 2809 .ops = &clk_dyn_rcg_ops, 2810 2810 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 2811 2811 },