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kernel os linux

dt-bindings: clock: qcom: Add SM8650 video clock controller

SM8650 video clock controller has most clocks same as SM8450,
but it also has few additional clocks and resets. Add device tree
bindings for the video clock controller on Qualcomm SM8650 platform
by defining these additional clocks and resets on top of SM8450.

Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240602114439.1611-3-quic_jkona@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Jagadeesh Kona and committed by
Bjorn Andersson
a6a61b97 213e1b58

+28 -1
+5 -1
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
··· 8 8 9 9 maintainers: 10 10 - Taniya Das <quic_tdas@quicinc.com> 11 + - Jagadeesh Kona <quic_jkona@quicinc.com> 11 12 12 13 description: | 13 14 Qualcomm video clock control module provides the clocks, resets and power 14 15 domains on SM8450. 15 16 16 - See also: include/dt-bindings/clock/qcom,sm8450-videocc.h 17 + See also: 18 + include/dt-bindings/clock/qcom,sm8450-videocc.h 19 + include/dt-bindings/clock/qcom,sm8650-videocc.h 17 20 18 21 properties: 19 22 compatible: 20 23 enum: 21 24 - qcom,sm8450-videocc 22 25 - qcom,sm8550-videocc 26 + - qcom,sm8650-videocc 23 27 24 28 reg: 25 29 maxItems: 1
+23
include/dt-bindings/clock/qcom,sm8650-videocc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H 7 + #define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H 8 + 9 + #include "qcom,sm8450-videocc.h" 10 + 11 + /* SM8650 introduces below new clocks and resets compared to SM8450 */ 12 + 13 + /* VIDEO_CC clocks */ 14 + #define VIDEO_CC_MVS0_SHIFT_CLK 12 15 + #define VIDEO_CC_MVS0C_SHIFT_CLK 13 16 + #define VIDEO_CC_MVS1_SHIFT_CLK 14 17 + #define VIDEO_CC_MVS1C_SHIFT_CLK 15 18 + #define VIDEO_CC_XO_CLK_SRC 16 19 + 20 + /* VIDEO_CC resets */ 21 + #define VIDEO_CC_XO_CLK_ARES 7 22 + 23 + #endif