tty/synclink: remove leftover bits of non-PCI card support

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Since commit 1355cba9c3ba ("tty/synclink: remove ISA support"), the
synlink driver only supports PCI card. Remove any leftover dead code
to support other cards.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lore.kernel.org/r/20200727130501.31005-1-hch@lst.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Christoph Hellwig and committed by

Greg Kroah-Hartman 5 years ago a5e0691f a3241891

+109 -241

1 changed file

expand all

drivers

tty

synclink.c

+109 -241

drivers/tty/synclink.c

··· 252 252 253 253 char device_name[25]; /* device instance name */ 254 254 255 - unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ 256 255 unsigned char bus; /* expansion bus number (zero based) */ 257 256 unsigned char function; /* PCI device number */ 258 257 ··· 3431 3432 char stat_buf[30]; 3432 3433 unsigned long flags; 3433 3434 3434 - if (info->bus_type == MGSL_BUS_TYPE_PCI) { 3435 - seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X", 3436 - info->device_name, info->io_base, info->irq_level, 3437 - info->phys_memory_base, info->phys_lcr_base); 3438 - } else { 3439 - seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d", 3440 - info->device_name, info->io_base, 3441 - info->irq_level, info->dma_level); 3442 - } 3435 + seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X", 3436 + info->device_name, info->io_base, info->irq_level, 3437 + info->phys_memory_base, info->phys_lcr_base); 3443 3438 3444 3439 /* output current serial signal states */ 3445 3440 spin_lock_irqsave(&info->irq_spinlock,flags); ··· 3549 3556 if ( info->max_frame_size % DMABUFFERSIZE ) 3550 3557 BuffersPerFrame++; 3551 3558 3552 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 3553 - /* 3554 - * The PCI adapter has 256KBytes of shared memory to use. 3555 - * This is 64 PAGE_SIZE buffers. 3556 - * 3557 - * The first page is used for padding at this time so the 3558 - * buffer list does not begin at offset 0 of the PCI 3559 - * adapter's shared memory. 3560 - * 3561 - * The 2nd page is used for the buffer list. A 4K buffer 3562 - * list can hold 128 DMA_BUFFER structures at 32 bytes 3563 - * each. 3564 - * 3565 - * This leaves 62 4K pages. 3566 - * 3567 - * The next N pages are used for transmit frame(s). We 3568 - * reserve enough 4K page blocks to hold the required 3569 - * number of transmit dma buffers (num_tx_dma_buffers), 3570 - * each of MaxFrameSize size. 3571 - * 3572 - * Of the remaining pages (62-N), determine how many can 3573 - * be used to receive full MaxFrameSize inbound frames 3574 - */ 3575 - info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; 3576 - info->rx_buffer_count = 62 - info->tx_buffer_count; 3577 - } else { 3578 - /* Calculate the number of PAGE_SIZE buffers needed for */ 3579 - /* receive and transmit DMA buffers. */ 3580 - 3581 - 3582 - /* Calculate the number of DMA buffers necessary to */ 3583 - /* hold 7 max size receive frames and one max size transmit frame. */ 3584 - /* The receive buffer count is bumped by one so we avoid an */ 3585 - /* End of List condition if all receive buffers are used when */ 3586 - /* using linked list DMA buffers. */ 3587 - 3588 - info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; 3589 - info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6; 3590 - 3591 - /* 3592 - * limit total TxBuffers & RxBuffers to 62 4K total 3593 - * (ala PCI Allocation) 3594 - */ 3595 - 3596 - if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 ) 3597 - info->rx_buffer_count = 62 - info->tx_buffer_count; 3598 - 3599 - } 3559 + /* 3560 + * The PCI adapter has 256KBytes of shared memory to use. This is 64 3561 + * PAGE_SIZE buffers. 3562 + * 3563 + * The first page is used for padding at this time so the buffer list 3564 + * does not begin at offset 0 of the PCI adapter's shared memory. 3565 + * 3566 + * The 2nd page is used for the buffer list. A 4K buffer list can hold 3567 + * 128 DMA_BUFFER structures at 32 bytes each. 3568 + * 3569 + * This leaves 62 4K pages. 3570 + * 3571 + * The next N pages are used for transmit frame(s). We reserve enough 3572 + * 4K page blocks to hold the required number of transmit dma buffers 3573 + * (num_tx_dma_buffers), each of MaxFrameSize size. 3574 + * 3575 + * Of the remaining pages (62-N), determine how many can be used to 3576 + * receive full MaxFrameSize inbound frames 3577 + */ 3578 + info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; 3579 + info->rx_buffer_count = 62 - info->tx_buffer_count; 3600 3580 3601 3581 if ( debug_level >= DEBUG_LEVEL_INFO ) 3602 3582 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n", ··· 3618 3652 { 3619 3653 unsigned int i; 3620 3654 3621 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 3622 - /* PCI adapter uses shared memory. */ 3623 - info->buffer_list = info->memory_base + info->last_mem_alloc; 3624 - info->buffer_list_phys = info->last_mem_alloc; 3625 - info->last_mem_alloc += BUFFERLISTSIZE; 3626 - } else { 3627 - /* ISA adapter uses system memory. */ 3628 - /* The buffer lists are allocated as a common buffer that both */ 3629 - /* the processor and adapter can access. This allows the driver to */ 3630 - /* inspect portions of the buffer while other portions are being */ 3631 - /* updated by the adapter using Bus Master DMA. */ 3632 - 3633 - info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL); 3634 - if (info->buffer_list == NULL) 3635 - return -ENOMEM; 3636 - info->buffer_list_phys = (u32)(info->buffer_list_dma_addr); 3637 - } 3655 + /* PCI adapter uses shared memory. */ 3656 + info->buffer_list = info->memory_base + info->last_mem_alloc; 3657 + info->buffer_list_phys = info->last_mem_alloc; 3658 + info->last_mem_alloc += BUFFERLISTSIZE; 3638 3659 3639 3660 /* We got the memory for the buffer entry lists. */ 3640 3661 /* Initialize the memory block to all zeros. */ ··· 3687 3734 */ 3688 3735 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info ) 3689 3736 { 3690 - if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI) 3691 - dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr); 3692 - 3693 3737 info->buffer_list = NULL; 3694 3738 info->rx_buffer_list = NULL; 3695 3739 info->tx_buffer_list = NULL; ··· 3712 3762 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount) 3713 3763 { 3714 3764 int i; 3715 - u32 phys_addr; 3716 3765 3717 3766 /* Allocate page sized buffers for the receive buffer list */ 3718 3767 3719 3768 for ( i = 0; i < Buffercount; i++ ) { 3720 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 3721 - /* PCI adapter uses shared memory buffers. */ 3722 - BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc; 3723 - phys_addr = info->last_mem_alloc; 3724 - info->last_mem_alloc += DMABUFFERSIZE; 3725 - } else { 3726 - /* ISA adapter uses system memory. */ 3727 - BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL); 3728 - if (BufferList[i].virt_addr == NULL) 3729 - return -ENOMEM; 3730 - phys_addr = (u32)(BufferList[i].dma_addr); 3731 - } 3732 - BufferList[i].phys_addr = phys_addr; 3769 + BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc; 3770 + BufferList[i].phys_addr = info->last_mem_alloc; 3771 + info->last_mem_alloc += DMABUFFERSIZE; 3733 3772 } 3734 3773 3735 3774 return 0; ··· 3746 3807 if ( BufferList ) { 3747 3808 for ( i = 0 ; i < Buffercount ; i++ ) { 3748 3809 if ( BufferList[i].virt_addr ) { 3749 - if ( info->bus_type != MGSL_BUS_TYPE_PCI ) 3750 - dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr); 3751 3810 BufferList[i].virt_addr = NULL; 3752 3811 } 3753 3812 } ··· 3977 4040 } 3978 4041 info->irq_requested = true; 3979 4042 3980 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 3981 - if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { 3982 - printk( "%s(%d):mem addr conflict device %s Addr=%08X\n", 3983 - __FILE__,__LINE__,info->device_name, info->phys_memory_base); 3984 - goto errout; 3985 - } 3986 - info->shared_mem_requested = true; 3987 - if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { 3988 - printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", 3989 - __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); 3990 - goto errout; 3991 - } 3992 - info->lcr_mem_requested = true; 3993 - 3994 - info->memory_base = ioremap(info->phys_memory_base, 3995 - 0x40000); 3996 - if (!info->memory_base) { 3997 - printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n", 3998 - __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 3999 - goto errout; 4000 - } 4001 - 4002 - if ( !mgsl_memory_test(info) ) { 4003 - printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n", 4004 - __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 4005 - goto errout; 4006 - } 4007 - 4008 - info->lcr_base = ioremap(info->phys_lcr_base, 4009 - PAGE_SIZE); 4010 - if (!info->lcr_base) { 4011 - printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n", 4012 - __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); 4013 - goto errout; 4014 - } 4015 - info->lcr_base += info->lcr_offset; 4016 - 4017 - } else { 4018 - /* claim DMA channel */ 4019 - 4020 - if (request_dma(info->dma_level,info->device_name) < 0){ 4021 - printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n", 4022 - __FILE__,__LINE__,info->device_name, info->dma_level ); 4023 - goto errout; 4024 - } 4025 - info->dma_requested = true; 4026 - 4027 - /* ISA adapter uses bus master DMA */ 4028 - set_dma_mode(info->dma_level,DMA_MODE_CASCADE); 4029 - enable_dma(info->dma_level); 4043 + if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { 4044 + printk( "%s(%d):mem addr conflict device %s Addr=%08X\n", 4045 + __FILE__,__LINE__,info->device_name, info->phys_memory_base); 4046 + goto errout; 4030 4047 } 4031 - 4048 + info->shared_mem_requested = true; 4049 + if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { 4050 + printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", 4051 + __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); 4052 + goto errout; 4053 + } 4054 + info->lcr_mem_requested = true; 4055 + 4056 + info->memory_base = ioremap(info->phys_memory_base, 0x40000); 4057 + if (!info->memory_base) { 4058 + printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n", 4059 + __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 4060 + goto errout; 4061 + } 4062 + 4063 + if ( !mgsl_memory_test(info) ) { 4064 + printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n", 4065 + __FILE__,__LINE__,info->device_name, info->phys_memory_base ); 4066 + goto errout; 4067 + } 4068 + 4069 + info->lcr_base = ioremap(info->phys_lcr_base, PAGE_SIZE); 4070 + if (!info->lcr_base) { 4071 + printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n", 4072 + __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); 4073 + goto errout; 4074 + } 4075 + info->lcr_base += info->lcr_offset; 4076 + 4032 4077 if ( mgsl_allocate_dma_buffers(info) < 0 ) { 4033 4078 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n", 4034 4079 __FILE__,__LINE__,info->device_name, info->dma_level ); ··· 4119 4200 else if ( info->max_frame_size > 65535 ) 4120 4201 info->max_frame_size = 65535; 4121 4202 4122 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 4123 - printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n", 4124 - info->hw_version + 1, info->device_name, info->io_base, info->irq_level, 4125 - info->phys_memory_base, info->phys_lcr_base, 4126 - info->max_frame_size ); 4127 - } else { 4128 - printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n", 4129 - info->device_name, info->io_base, info->irq_level, info->dma_level, 4130 - info->max_frame_size ); 4131 - } 4203 + printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n", 4204 + info->hw_version + 1, info->device_name, info->io_base, info->irq_level, 4205 + info->phys_memory_base, info->phys_lcr_base, 4206 + info->max_frame_size ); 4132 4207 4133 4208 #if SYNCLINK_GENERIC_HDLC 4134 4209 hdlcdev_init(info); ··· 4333 4420 outw( Cmd + info->loopback_bits, info->io_base + CCAR ); 4334 4421 4335 4422 /* Read to flush write to CCAR */ 4336 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4337 - inw( info->io_base + CCAR ); 4423 + inw( info->io_base + CCAR ); 4338 4424 4339 4425 } /* end of usc_RTCmd() */ 4340 4426 ··· 4357 4445 outw( Cmd + info->mbre_bit, info->io_base ); 4358 4446 4359 4447 /* Read to flush write to DCAR */ 4360 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4361 - inw( info->io_base ); 4448 + inw( info->io_base ); 4362 4449 4363 4450 } /* end of usc_DmaCmd() */ 4364 4451 ··· 4386 4475 outw( RegValue, info->io_base ); 4387 4476 4388 4477 /* Read to flush write to DCAR */ 4389 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4390 - inw( info->io_base ); 4478 + inw( info->io_base ); 4391 4479 4392 4480 } /* end of usc_OutDmaReg() */ 4393 4481 ··· 4438 4528 outw( RegValue, info->io_base + CCAR ); 4439 4529 4440 4530 /* Read to flush write to CCAR */ 4441 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4442 - inw( info->io_base + CCAR ); 4531 + inw( info->io_base + CCAR ); 4443 4532 4444 4533 } /* end of usc_OutReg() */ 4445 4534 ··· 4637 4728 4638 4729 RegValue = usc_InReg( info, RICR ) & 0xc0; 4639 4730 4640 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4641 - usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); 4642 - else 4643 - usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); 4731 + usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); 4644 4732 4645 4733 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */ 4646 4734 ··· 4698 4792 * 0000 0000 0011 0110 = 0x0036 4699 4793 */ 4700 4794 4701 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4702 - usc_OutReg( info, TICR, 0x0736 ); 4703 - else 4704 - usc_OutReg( info, TICR, 0x1436 ); 4795 + usc_OutReg( info, TICR, 0x0736 ); 4705 4796 4706 4797 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); 4707 4798 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); ··· 4788 4885 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */ 4789 4886 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */ 4790 4887 4791 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 4792 - XtalSpeed = 11059200; 4793 - else 4794 - XtalSpeed = 14745600; 4888 + XtalSpeed = 11059200; 4795 4889 4796 4890 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { 4797 4891 DpllDivisor = 16; ··· 4911 5011 * 0110 0000 0000 1011 = 0x600b 4912 5012 */ 4913 5013 4914 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 4915 - /* PCI adapter does not need DMA wait state */ 4916 - usc_OutDmaReg( info, DCR, 0xa00b ); 4917 - } 4918 - else 4919 - usc_OutDmaReg( info, DCR, 0x800b ); 4920 - 5014 + /* PCI adapter does not need DMA wait state */ 5015 + usc_OutDmaReg( info, DCR, 0xa00b ); 4921 5016 4922 5017 /* Receive DMA mode Register (RDMR) 4923 5018 * ··· 5004 5109 * <7..0> 0x00 Maximum number of clock cycles per bus grant 5005 5110 */ 5006 5111 5007 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 5008 - /* don't limit bus occupancy on PCI adapter */ 5009 - usc_OutDmaReg( info, BDCR, 0x0000 ); 5010 - } 5011 - else 5012 - usc_OutDmaReg( info, BDCR, 0x2000 ); 5112 + /* don't limit bus occupancy on PCI adapter */ 5113 + usc_OutDmaReg( info, BDCR, 0x0000 ); 5013 5114 5014 5115 usc_stop_transmitter(info); 5015 5116 usc_stop_receiver(info); ··· 5046 5155 /* Write 16-bit Time Constant for BRG0 */ 5047 5156 /* use clock speed if available, otherwise use 8 for diagnostics */ 5048 5157 if (info->params.clock_speed) { 5049 - if (info->bus_type == MGSL_BUS_TYPE_PCI) 5050 - usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); 5051 - else 5052 - usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1)); 5158 + usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); 5053 5159 } else 5054 5160 usc_OutReg(info, TC0R, (u16)8); 5055 5161 ··· 5089 5201 u16 Tc; 5090 5202 5091 5203 if ( data_rate ) { 5092 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 5093 - XtalSpeed = 11059200; 5094 - else 5095 - XtalSpeed = 14745600; 5204 + XtalSpeed = 11059200; 5096 5205 5097 5206 5098 5207 /* Tc = (Xtal/Speed) - 1 */ ··· 5567 5682 */ 5568 5683 static void usc_reset( struct mgsl_struct *info ) 5569 5684 { 5570 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { 5571 - int i; 5572 - u32 readval; 5685 + int i; 5686 + u32 readval; 5573 5687 5574 - /* Set BIT30 of Misc Control Register */ 5575 - /* (Local Control Register 0x50) to force reset of USC. */ 5688 + /* Set BIT30 of Misc Control Register */ 5689 + /* (Local Control Register 0x50) to force reset of USC. */ 5576 5690 5577 - volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); 5578 - u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28); 5691 + volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); 5692 + u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28); 5579 5693 5580 - info->misc_ctrl_value |= BIT30; 5581 - *MiscCtrl = info->misc_ctrl_value; 5694 + info->misc_ctrl_value |= BIT30; 5695 + *MiscCtrl = info->misc_ctrl_value; 5582 5696 5583 - /* 5584 - * Force at least 170ns delay before clearing 5585 - * reset bit. Each read from LCR takes at least 5586 - * 30ns so 10 times for 300ns to be safe. 5587 - */ 5588 - for(i=0;i<10;i++) 5589 - readval = *MiscCtrl; 5697 + /* 5698 + * Force at least 170ns delay before clearing reset bit. Each read from 5699 + * LCR takes at least 30ns so 10 times for 300ns to be safe. 5700 + */ 5701 + for(i=0;i<10;i++) 5702 + readval = *MiscCtrl; 5590 5703 5591 - info->misc_ctrl_value &= ~BIT30; 5592 - *MiscCtrl = info->misc_ctrl_value; 5704 + info->misc_ctrl_value &= ~BIT30; 5705 + *MiscCtrl = info->misc_ctrl_value; 5593 5706 5594 - *LCR0BRDR = BUS_DESCRIPTOR( 5595 - 1, // Write Strobe Hold (0-3) 5596 - 2, // Write Strobe Delay (0-3) 5597 - 2, // Read Strobe Delay (0-3) 5598 - 0, // NWDD (Write data-data) (0-3) 5599 - 4, // NWAD (Write Addr-data) (0-31) 5600 - 0, // NXDA (Read/Write Data-Addr) (0-3) 5601 - 0, // NRDD (Read Data-Data) (0-3) 5602 - 5 // NRAD (Read Addr-Data) (0-31) 5603 - ); 5604 - } else { 5605 - /* do HW reset */ 5606 - outb( 0,info->io_base + 8 ); 5607 - } 5707 + *LCR0BRDR = BUS_DESCRIPTOR( 5708 + 1, // Write Strobe Hold (0-3) 5709 + 2, // Write Strobe Delay (0-3) 5710 + 2, // Read Strobe Delay (0-3) 5711 + 0, // NWDD (Write data-data) (0-3) 5712 + 4, // NWAD (Write Addr-data) (0-31) 5713 + 0, // NXDA (Read/Write Data-Addr) (0-3) 5714 + 0, // NRDD (Read Data-Data) (0-3) 5715 + 5 // NRAD (Read Addr-Data) (0-31) 5716 + ); 5608 5717 5609 5718 info->mbre_bit = 0; 5610 5719 info->loopback_bits = 0; ··· 6107 6228 * ClkSpeed = 921600 (ISA), 691200 (PCI) 6108 6229 */ 6109 6230 6110 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 6111 - usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) ); 6112 - else 6113 - usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) ); 6114 - 6231 + usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) ); 6115 6232 6116 6233 /* 6117 6234 * Hardware Configuration Register (HCR) ··· 6712 6837 6713 6838 /* Actually copy data from source buffer to DMA buffer. */ 6714 6839 /* Also set the data count for this individual DMA buffer. */ 6715 - if ( info->bus_type == MGSL_BUS_TYPE_PCI ) 6716 - mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount); 6717 - else 6718 - memcpy(pBufEntry->virt_addr, Buffer, Copycount); 6840 + mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount); 6719 6841 6720 6842 pBufEntry->count = Copycount; 6721 6843 ··· 7186 7314 unsigned long i; 7187 7315 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long); 7188 7316 unsigned long * TestAddr; 7189 - 7190 - if ( info->bus_type != MGSL_BUS_TYPE_PCI ) 7191 - return true; 7192 7317 7193 7318 TestAddr = (unsigned long *)info->memory_base; 7194 7319 ··· 7872 8003 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); 7873 8004 info->phys_lcr_base &= ~(PAGE_SIZE-1); 7874 8005 7875 - info->bus_type = MGSL_BUS_TYPE_PCI; 7876 8006 info->io_addr_size = 8; 7877 8007 info->irq_flags = IRQF_SHARED; 7878 8008