tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/nouveau: Rework tile region handling.

The point is to share more code between the PFB/PGRAPH tile region
hooks, and give the hardware specific functions a chance to allocate
per-region resources.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

authored by

Francisco Jerez and committed by
Ben Skeggs a5cf68b0 e419cf09

+219 -158
+4 -7
drivers/gpu/drm/nouveau/nouveau_bo.c
··· 46 46 if (unlikely(nvbo->gem)) 47 47 DRM_ERROR("bo %p still attached to GEM object\n", bo); 48 48 49 - if (nvbo->tile) 50 - nv10_mem_expire_tiling(dev, nvbo->tile, NULL); 51 - 49 + nv10_mem_put_tile_region(dev, nvbo->tile, NULL); 52 50 kfree(nvbo); 53 51 } 54 52 ··· 790 792 791 793 } else if (dev_priv->card_type >= NV_10) { 792 794 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, 793 - nvbo->tile_mode); 795 + nvbo->tile_mode, 796 + nvbo->tile_flags); 794 797 } 795 798 796 799 return 0; ··· 807 808 808 809 if (dev_priv->card_type >= NV_10 && 809 810 dev_priv->card_type < NV_50) { 810 - if (*old_tile) 811 - nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); 812 - 811 + nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj); 813 812 *old_tile = new_tile; 814 813 } 815 814 }
+34 -25
drivers/gpu/drm/nouveau/nouveau_drv.h
··· 66 66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 67 68 68 struct nouveau_tile_reg { 69 - struct nouveau_fence *fence; 70 - uint32_t addr; 71 - uint32_t size; 72 69 bool used; 70 + uint32_t addr; 71 + uint32_t limit; 72 + uint32_t pitch; 73 + struct nouveau_fence *fence; 73 74 }; 74 75 75 76 struct nouveau_bo { ··· 310 309 int (*init)(struct drm_device *dev); 311 310 void (*takedown)(struct drm_device *dev); 312 311 313 - void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 314 - uint32_t size, uint32_t pitch); 312 + void (*init_tile_region)(struct drm_device *dev, int i, 313 + uint32_t addr, uint32_t size, 314 + uint32_t pitch, uint32_t flags); 315 + void (*set_tile_region)(struct drm_device *dev, int i); 316 + void (*free_tile_region)(struct drm_device *dev, int i); 315 317 }; 316 318 317 319 struct nouveau_fifo_engine { ··· 360 356 int (*unload_context)(struct drm_device *); 361 357 void (*tlb_flush)(struct drm_device *dev); 362 358 363 - void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 364 - uint32_t size, uint32_t pitch); 359 + void (*set_tile_region)(struct drm_device *dev, int i); 365 360 }; 366 361 367 362 struct nouveau_display_engine { ··· 671 668 } gart_info; 672 669 673 670 /* nv10-nv40 tiling regions */ 674 - struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 671 + struct { 672 + struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 673 + spinlock_t lock; 674 + } tile; 675 675 676 676 /* VRAM/fb configuration */ 677 677 uint64_t vram_size; ··· 804 798 extern int nouveau_mem_init_agp(struct drm_device *); 805 799 extern int nouveau_mem_reset_agp(struct drm_device *); 806 800 extern void nouveau_mem_close(struct drm_device *); 807 - extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 808 - uint32_t addr, 809 - uint32_t size, 810 - uint32_t pitch); 811 - extern void nv10_mem_expire_tiling(struct drm_device *dev, 812 - struct nouveau_tile_reg *tile, 813 - struct nouveau_fence *fence); 801 + extern struct nouveau_tile_reg *nv10_mem_set_tiling( 802 + struct drm_device *dev, uint32_t addr, uint32_t size, 803 + uint32_t pitch, uint32_t flags); 804 + extern void nv10_mem_put_tile_region(struct drm_device *dev, 805 + struct nouveau_tile_reg *tile, 806 + struct nouveau_fence *fence); 814 807 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 815 808 uint32_t size, uint32_t flags, 816 809 uint64_t phys); ··· 1016 1011 /* nv10_fb.c */ 1017 1012 extern int nv10_fb_init(struct drm_device *); 1018 1013 extern void nv10_fb_takedown(struct drm_device *); 1019 - extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 1020 - uint32_t, uint32_t); 1014 + extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1015 + uint32_t addr, uint32_t size, 1016 + uint32_t pitch, uint32_t flags); 1017 + extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1018 + extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1021 1019 1022 1020 /* nv30_fb.c */ 1023 1021 extern int nv30_fb_init(struct drm_device *); 1024 1022 extern void nv30_fb_takedown(struct drm_device *); 1023 + extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1024 + uint32_t addr, uint32_t size, 1025 + uint32_t pitch, uint32_t flags); 1026 + extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1025 1027 1026 1028 /* nv40_fb.c */ 1027 1029 extern int nv40_fb_init(struct drm_device *); 1028 1030 extern void nv40_fb_takedown(struct drm_device *); 1029 - extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 1030 - uint32_t, uint32_t); 1031 + extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1032 + 1031 1033 /* nv50_fb.c */ 1032 1034 extern int nv50_fb_init(struct drm_device *); 1033 1035 extern void nv50_fb_takedown(struct drm_device *); ··· 1114 1102 extern int nv10_graph_load_context(struct nouveau_channel *); 1115 1103 extern int nv10_graph_unload_context(struct drm_device *); 1116 1104 extern void nv10_graph_context_switch(struct drm_device *); 1117 - extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1118 - uint32_t, uint32_t); 1105 + extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1119 1106 1120 1107 /* nv20_graph.c */ 1121 1108 extern int nv20_graph_create_context(struct nouveau_channel *); ··· 1124 1113 extern int nv20_graph_init(struct drm_device *); 1125 1114 extern void nv20_graph_takedown(struct drm_device *); 1126 1115 extern int nv30_graph_init(struct drm_device *); 1127 - extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1128 - uint32_t, uint32_t); 1116 + extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1129 1117 1130 1118 /* nv40_graph.c */ 1131 1119 extern int nv40_graph_init(struct drm_device *); ··· 1135 1125 extern int nv40_graph_load_context(struct nouveau_channel *); 1136 1126 extern int nv40_graph_unload_context(struct drm_device *); 1137 1127 extern void nv40_grctx_init(struct nouveau_grctx *); 1138 - extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1139 - uint32_t, uint32_t); 1128 + extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1140 1129 1141 1130 /* nv50_graph.c */ 1142 1131 extern int nv50_graph_init(struct drm_device *);
+66 -45
drivers/gpu/drm/nouveau/nouveau_mem.c
··· 42 42 */ 43 43 44 44 static void 45 - nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 46 - uint32_t size, uint32_t pitch) 45 + nv10_mem_update_tile_region(struct drm_device *dev, 46 + struct nouveau_tile_reg *tile, uint32_t addr, 47 + uint32_t size, uint32_t pitch, uint32_t flags) 47 48 { 48 49 struct drm_nouveau_private *dev_priv = dev->dev_private; 49 50 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 50 51 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 51 52 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 52 - struct nouveau_tile_reg *tile = &dev_priv->tile[i]; 53 + int i = tile - dev_priv->tile.reg; 54 + unsigned long save; 53 55 54 - tile->addr = addr; 55 - tile->size = size; 56 - tile->used = !!pitch; 57 56 nouveau_fence_unref(&tile->fence); 58 57 58 + if (tile->pitch) 59 + pfb->free_tile_region(dev, i); 60 + 61 + if (pitch) 62 + pfb->init_tile_region(dev, i, addr, size, pitch, flags); 63 + 64 + spin_lock_irqsave(&dev_priv->context_switch_lock, save); 59 65 pfifo->reassign(dev, false); 60 66 pfifo->cache_pull(dev, false); 61 67 62 68 nouveau_wait_for_idle(dev); 63 69 64 - pgraph->set_region_tiling(dev, i, addr, size, pitch); 65 - pfb->set_region_tiling(dev, i, addr, size, pitch); 70 + pfb->set_tile_region(dev, i); 71 + pgraph->set_tile_region(dev, i); 66 72 67 73 pfifo->cache_pull(dev, true); 68 74 pfifo->reassign(dev, true); 75 + spin_unlock_irqrestore(&dev_priv->context_switch_lock, save); 76 + } 77 + 78 + static struct nouveau_tile_reg * 79 + nv10_mem_get_tile_region(struct drm_device *dev, int i) 80 + { 81 + struct drm_nouveau_private *dev_priv = dev->dev_private; 82 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 83 + 84 + spin_lock(&dev_priv->tile.lock); 85 + 86 + if (!tile->used && 87 + (!tile->fence || nouveau_fence_signalled(tile->fence))) 88 + tile->used = true; 89 + else 90 + tile = NULL; 91 + 92 + spin_unlock(&dev_priv->tile.lock); 93 + return tile; 94 + } 95 + 96 + void 97 + nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile, 98 + struct nouveau_fence *fence) 99 + { 100 + struct drm_nouveau_private *dev_priv = dev->dev_private; 101 + 102 + if (tile) { 103 + spin_lock(&dev_priv->tile.lock); 104 + if (fence) { 105 + /* Mark it as pending. */ 106 + tile->fence = fence; 107 + nouveau_fence_ref(fence); 108 + } 109 + 110 + tile->used = false; 111 + spin_unlock(&dev_priv->tile.lock); 112 + } 69 113 } 70 114 71 115 struct nouveau_tile_reg * 72 116 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, 73 - uint32_t pitch) 117 + uint32_t pitch, uint32_t flags) 74 118 { 75 119 struct drm_nouveau_private *dev_priv = dev->dev_private; 76 120 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 77 - struct nouveau_tile_reg *found = NULL; 78 - unsigned long i, flags; 79 - 80 - spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 121 + struct nouveau_tile_reg *tile, *found = NULL; 122 + int i; 81 123 82 124 for (i = 0; i < pfb->num_tiles; i++) { 83 - struct nouveau_tile_reg *tile = &dev_priv->tile[i]; 84 - 85 - if (tile->used) 86 - /* Tile region in use. */ 87 - continue; 88 - 89 - if (tile->fence && 90 - !nouveau_fence_signalled(tile->fence)) 91 - /* Pending tile region. */ 92 - continue; 93 - 94 - if (max(tile->addr, addr) < 95 - min(tile->addr + tile->size, addr + size)) 96 - /* Kill an intersecting tile region. */ 97 - nv10_mem_set_region_tiling(dev, i, 0, 0, 0); 125 + tile = nv10_mem_get_tile_region(dev, i); 98 126 99 127 if (pitch && !found) { 100 - /* Free tile region. */ 101 - nv10_mem_set_region_tiling(dev, i, addr, size, pitch); 102 128 found = tile; 129 + continue; 130 + 131 + } else if (tile && tile->pitch) { 132 + /* Kill an unused tile region. */ 133 + nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0); 103 134 } 135 + 136 + nv10_mem_put_tile_region(dev, tile, NULL); 104 137 } 105 138 106 - spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 107 - 139 + if (found) 140 + nv10_mem_update_tile_region(dev, found, addr, size, 141 + pitch, flags); 108 142 return found; 109 - } 110 - 111 - void 112 - nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile, 113 - struct nouveau_fence *fence) 114 - { 115 - if (fence) { 116 - /* Mark it as pending. */ 117 - tile->fence = fence; 118 - nouveau_fence_ref(fence); 119 - } 120 - 121 - tile->used = false; 122 143 } 123 144 124 145 /*
+17 -8
drivers/gpu/drm/nouveau/nouveau_state.c
··· 118 118 engine->timer.takedown = nv04_timer_takedown; 119 119 engine->fb.init = nv10_fb_init; 120 120 engine->fb.takedown = nv10_fb_takedown; 121 - engine->fb.set_region_tiling = nv10_fb_set_region_tiling; 121 + engine->fb.init_tile_region = nv10_fb_init_tile_region; 122 + engine->fb.set_tile_region = nv10_fb_set_tile_region; 123 + engine->fb.free_tile_region = nv10_fb_free_tile_region; 122 124 engine->graph.init = nv10_graph_init; 123 125 engine->graph.takedown = nv10_graph_takedown; 124 126 engine->graph.channel = nv10_graph_channel; ··· 129 127 engine->graph.fifo_access = nv04_graph_fifo_access; 130 128 engine->graph.load_context = nv10_graph_load_context; 131 129 engine->graph.unload_context = nv10_graph_unload_context; 132 - engine->graph.set_region_tiling = nv10_graph_set_region_tiling; 130 + engine->graph.set_tile_region = nv10_graph_set_tile_region; 133 131 engine->fifo.channels = 32; 134 132 engine->fifo.init = nv10_fifo_init; 135 133 engine->fifo.takedown = nouveau_stub_takedown; ··· 175 173 engine->timer.takedown = nv04_timer_takedown; 176 174 engine->fb.init = nv10_fb_init; 177 175 engine->fb.takedown = nv10_fb_takedown; 178 - engine->fb.set_region_tiling = nv10_fb_set_region_tiling; 176 + engine->fb.init_tile_region = nv10_fb_init_tile_region; 177 + engine->fb.set_tile_region = nv10_fb_set_tile_region; 178 + engine->fb.free_tile_region = nv10_fb_free_tile_region; 179 179 engine->graph.init = nv20_graph_init; 180 180 engine->graph.takedown = nv20_graph_takedown; 181 181 engine->graph.channel = nv10_graph_channel; ··· 186 182 engine->graph.fifo_access = nv04_graph_fifo_access; 187 183 engine->graph.load_context = nv20_graph_load_context; 188 184 engine->graph.unload_context = nv20_graph_unload_context; 189 - engine->graph.set_region_tiling = nv20_graph_set_region_tiling; 185 + engine->graph.set_tile_region = nv20_graph_set_tile_region; 190 186 engine->fifo.channels = 32; 191 187 engine->fifo.init = nv10_fifo_init; 192 188 engine->fifo.takedown = nouveau_stub_takedown; ··· 232 228 engine->timer.takedown = nv04_timer_takedown; 233 229 engine->fb.init = nv30_fb_init; 234 230 engine->fb.takedown = nv30_fb_takedown; 235 - engine->fb.set_region_tiling = nv10_fb_set_region_tiling; 231 + engine->fb.init_tile_region = nv30_fb_init_tile_region; 232 + engine->fb.set_tile_region = nv10_fb_set_tile_region; 233 + engine->fb.free_tile_region = nv30_fb_free_tile_region; 236 234 engine->graph.init = nv30_graph_init; 237 235 engine->graph.takedown = nv20_graph_takedown; 238 236 engine->graph.fifo_access = nv04_graph_fifo_access; ··· 243 237 engine->graph.destroy_context = nv20_graph_destroy_context; 244 238 engine->graph.load_context = nv20_graph_load_context; 245 239 engine->graph.unload_context = nv20_graph_unload_context; 246 - engine->graph.set_region_tiling = nv20_graph_set_region_tiling; 240 + engine->graph.set_tile_region = nv20_graph_set_tile_region; 247 241 engine->fifo.channels = 32; 248 242 engine->fifo.init = nv10_fifo_init; 249 243 engine->fifo.takedown = nouveau_stub_takedown; ··· 292 286 engine->timer.takedown = nv04_timer_takedown; 293 287 engine->fb.init = nv40_fb_init; 294 288 engine->fb.takedown = nv40_fb_takedown; 295 - engine->fb.set_region_tiling = nv40_fb_set_region_tiling; 289 + engine->fb.init_tile_region = nv30_fb_init_tile_region; 290 + engine->fb.set_tile_region = nv40_fb_set_tile_region; 291 + engine->fb.free_tile_region = nv30_fb_free_tile_region; 296 292 engine->graph.init = nv40_graph_init; 297 293 engine->graph.takedown = nv40_graph_takedown; 298 294 engine->graph.fifo_access = nv04_graph_fifo_access; ··· 303 295 engine->graph.destroy_context = nv40_graph_destroy_context; 304 296 engine->graph.load_context = nv40_graph_load_context; 305 297 engine->graph.unload_context = nv40_graph_unload_context; 306 - engine->graph.set_region_tiling = nv40_graph_set_region_tiling; 298 + engine->graph.set_tile_region = nv40_graph_set_tile_region; 307 299 engine->fifo.channels = 32; 308 300 engine->fifo.init = nv40_fifo_init; 309 301 engine->fifo.takedown = nouveau_stub_takedown; ··· 604 596 goto out; 605 597 engine = &dev_priv->engine; 606 598 spin_lock_init(&dev_priv->channels.lock); 599 + spin_lock_init(&dev_priv->tile.lock); 607 600 spin_lock_init(&dev_priv->context_switch_lock); 608 601 609 602 /* Make the CRTCs and I2C buses accessible */
+31 -13
drivers/gpu/drm/nouveau/nv10_fb.c
··· 4 4 #include "nouveau_drm.h" 5 5 6 6 void 7 - nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 8 - uint32_t size, uint32_t pitch) 7 + nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr, 8 + uint32_t size, uint32_t pitch, uint32_t flags) 9 9 { 10 10 struct drm_nouveau_private *dev_priv = dev->dev_private; 11 - uint32_t limit = max(1u, addr + size) - 1; 11 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 12 12 13 - if (pitch) { 14 - if (dev_priv->card_type >= NV_20) 15 - addr |= 1; 16 - else 17 - addr |= 1 << 31; 18 - } 13 + tile->addr = addr; 14 + tile->limit = max(1u, addr + size) - 1; 15 + tile->pitch = pitch; 19 16 20 - nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); 21 - nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); 22 - nv_wr32(dev, NV10_PFB_TILE(i), addr); 17 + if (dev_priv->card_type == NV_20) 18 + tile->addr |= 1; 19 + else 20 + tile->addr |= 1 << 31; 21 + } 22 + 23 + void 24 + nv10_fb_free_tile_region(struct drm_device *dev, int i) 25 + { 26 + struct drm_nouveau_private *dev_priv = dev->dev_private; 27 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 28 + 29 + tile->addr = tile->limit = tile->pitch = 0; 30 + } 31 + 32 + void 33 + nv10_fb_set_tile_region(struct drm_device *dev, int i) 34 + { 35 + struct drm_nouveau_private *dev_priv = dev->dev_private; 36 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 37 + 38 + nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); 39 + nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); 40 + nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); 23 41 } 24 42 25 43 int ··· 51 33 52 34 /* Turn all the tiling regions off. */ 53 35 for (i = 0; i < pfb->num_tiles; i++) 54 - pfb->set_region_tiling(dev, i, 0, 0, 0); 36 + pfb->set_tile_region(dev, i); 55 37 56 38 return 0; 57 39 }
+7 -10
drivers/gpu/drm/nouveau/nv10_graph.c
··· 899 899 } 900 900 901 901 void 902 - nv10_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 903 - uint32_t size, uint32_t pitch) 902 + nv10_graph_set_tile_region(struct drm_device *dev, int i) 904 903 { 905 - uint32_t limit = max(1u, addr + size) - 1; 904 + struct drm_nouveau_private *dev_priv = dev->dev_private; 905 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 906 906 907 - if (pitch) 908 - addr |= 1 << 31; 909 - 910 - nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), limit); 911 - nv_wr32(dev, NV10_PGRAPH_TSIZE(i), pitch); 912 - nv_wr32(dev, NV10_PGRAPH_TILE(i), addr); 907 + nv_wr32(dev, NV10_PGRAPH_TLIMIT(i), tile->limit); 908 + nv_wr32(dev, NV10_PGRAPH_TSIZE(i), tile->pitch); 909 + nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr); 913 910 } 914 911 915 912 int nv10_graph_init(struct drm_device *dev) ··· 946 949 947 950 /* Turn all the tiling regions off. */ 948 951 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 949 - nv10_graph_set_region_tiling(dev, i, 0, 0, 0); 952 + nv10_graph_set_tile_region(dev, i); 950 953 951 954 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); 952 955 nv_wr32(dev, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000);
+11 -14
drivers/gpu/drm/nouveau/nv20_graph.c
··· 511 511 } 512 512 513 513 void 514 - nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 515 - uint32_t size, uint32_t pitch) 514 + nv20_graph_set_tile_region(struct drm_device *dev, int i) 516 515 { 517 - uint32_t limit = max(1u, addr + size) - 1; 516 + struct drm_nouveau_private *dev_priv = dev->dev_private; 517 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 518 518 519 - if (pitch) 520 - addr |= 1; 521 - 522 - nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 523 - nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 524 - nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 519 + nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); 520 + nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); 521 + nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); 525 522 526 523 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); 527 - nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit); 524 + nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit); 528 525 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); 529 - nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch); 526 + nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch); 530 527 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); 531 - nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr); 528 + nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr); 532 529 } 533 530 534 531 int ··· 609 612 610 613 /* Turn all the tiling regions off. */ 611 614 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 612 - nv20_graph_set_region_tiling(dev, i, 0, 0, 0); 615 + nv20_graph_set_tile_region(dev, i); 613 616 614 617 for (i = 0; i < 8; i++) { 615 618 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4)); ··· 748 751 749 752 /* Turn all the tiling regions off. */ 750 753 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 751 - nv20_graph_set_region_tiling(dev, i, 0, 0, 0); 754 + nv20_graph_set_tile_region(dev, i); 752 755 753 756 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 754 757 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
+22 -1
drivers/gpu/drm/nouveau/nv30_fb.c
··· 29 29 #include "nouveau_drv.h" 30 30 #include "nouveau_drm.h" 31 31 32 + void 33 + nv30_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr, 34 + uint32_t size, uint32_t pitch, uint32_t flags) 35 + { 36 + struct drm_nouveau_private *dev_priv = dev->dev_private; 37 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 38 + 39 + tile->addr = addr | 1; 40 + tile->limit = max(1u, addr + size) - 1; 41 + tile->pitch = pitch; 42 + } 43 + 44 + void 45 + nv30_fb_free_tile_region(struct drm_device *dev, int i) 46 + { 47 + struct drm_nouveau_private *dev_priv = dev->dev_private; 48 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 49 + 50 + tile->addr = tile->limit = tile->pitch = 0; 51 + } 52 + 32 53 static int 33 54 calc_bias(struct drm_device *dev, int k, int i, int j) 34 55 { ··· 86 65 87 66 /* Turn all the tiling regions off. */ 88 67 for (i = 0; i < pfb->num_tiles; i++) 89 - pfb->set_region_tiling(dev, i, 0, 0, 0); 68 + pfb->set_tile_region(dev, i); 90 69 91 70 /* Init the memory timing regs at 0x10037c/0x1003ac */ 92 71 if (dev_priv->chipset == 0x30 ||
+9 -13
drivers/gpu/drm/nouveau/nv40_fb.c
··· 4 4 #include "nouveau_drm.h" 5 5 6 6 void 7 - nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 8 - uint32_t size, uint32_t pitch) 7 + nv40_fb_set_tile_region(struct drm_device *dev, int i) 9 8 { 10 9 struct drm_nouveau_private *dev_priv = dev->dev_private; 11 - uint32_t limit = max(1u, addr + size) - 1; 12 - 13 - if (pitch) 14 - addr |= 1; 10 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 15 11 16 12 switch (dev_priv->chipset) { 17 13 case 0x40: 18 - nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); 19 - nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); 20 - nv_wr32(dev, NV10_PFB_TILE(i), addr); 14 + nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); 15 + nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); 16 + nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); 21 17 break; 22 18 23 19 default: 24 - nv_wr32(dev, NV40_PFB_TLIMIT(i), limit); 25 - nv_wr32(dev, NV40_PFB_TSIZE(i), pitch); 26 - nv_wr32(dev, NV40_PFB_TILE(i), addr); 20 + nv_wr32(dev, NV40_PFB_TLIMIT(i), tile->limit); 21 + nv_wr32(dev, NV40_PFB_TSIZE(i), tile->pitch); 22 + nv_wr32(dev, NV40_PFB_TILE(i), tile->addr); 27 23 break; 28 24 } 29 25 } ··· 60 64 61 65 /* Turn all the tiling regions off. */ 62 66 for (i = 0; i < pfb->num_tiles; i++) 63 - pfb->set_region_tiling(dev, i, 0, 0, 0); 67 + pfb->set_tile_region(dev, i); 64 68 65 69 return 0; 66 70 }
+18 -22
drivers/gpu/drm/nouveau/nv40_graph.c
··· 192 192 } 193 193 194 194 void 195 - nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 196 - uint32_t size, uint32_t pitch) 195 + nv40_graph_set_tile_region(struct drm_device *dev, int i) 197 196 { 198 197 struct drm_nouveau_private *dev_priv = dev->dev_private; 199 - uint32_t limit = max(1u, addr + size) - 1; 200 - 201 - if (pitch) 202 - addr |= 1; 198 + struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 203 199 204 200 switch (dev_priv->chipset) { 205 201 case 0x44: 206 202 case 0x4a: 207 203 case 0x4e: 208 - nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 209 - nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 210 - nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 204 + nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); 205 + nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); 206 + nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); 211 207 break; 212 208 213 209 case 0x46: 214 210 case 0x47: 215 211 case 0x49: 216 212 case 0x4b: 217 - nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch); 218 - nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit); 219 - nv_wr32(dev, NV47_PGRAPH_TILE(i), addr); 220 - nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); 221 - nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); 222 - nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); 213 + nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch); 214 + nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit); 215 + nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr); 216 + nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch); 217 + nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); 218 + nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); 223 219 break; 224 220 225 221 default: 226 - nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 227 - nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 228 - nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 229 - nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); 230 - nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); 231 - nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); 222 + nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch); 223 + nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit); 224 + nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr); 225 + nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch); 226 + nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit); 227 + nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr); 232 228 break; 233 229 } 234 230 } ··· 365 369 366 370 /* Turn all the tiling regions off. */ 367 371 for (i = 0; i < pfb->num_tiles; i++) 368 - nv40_graph_set_region_tiling(dev, i, 0, 0, 0); 372 + nv40_graph_set_tile_region(dev, i); 369 373 370 374 /* begin RAM config */ 371 375 vramsz = pci_resource_len(dev->pdev, 0) - 1;