tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
OMAP3: PM: ensure IO wakeups are properly disabled
omap: Fix omap_4430sdp_defconfig for make oldconfig
omap: Use CONFIG_SMP for test_for_ipi and test_for_ltirq
omap: Fix sev instruction usage for multi-omap
OMAP3: Fix a cpu type check problem
omap3: id: fix 3630 rev detection

Linus Torvalds a5a82834 997396a7

+20 -20
unified split
+3
arch/arm/configs/omap_4430sdp_defconfig
··· 13 # CONFIG_BLK_DEV_BSG is not set 14 CONFIG_ARCH_OMAP=y 15 CONFIG_ARCH_OMAP4=y 16 # CONFIG_OMAP_MUX is not set 17 CONFIG_OMAP_32K_TIMER=y 18 CONFIG_OMAP_DM_TIMER=y
··· 13 # CONFIG_BLK_DEV_BSG is not set 14 CONFIG_ARCH_OMAP=y 15 CONFIG_ARCH_OMAP4=y 16 + # CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set 17 + # CONFIG_ARCH_OMAP2 is not set 18 + # CONFIG_ARCH_OMAP3 is not set 19 # CONFIG_OMAP_MUX is not set 20 CONFIG_OMAP_32K_TIMER=y 21 CONFIG_OMAP_DM_TIMER=y
+1
arch/arm/mach-omap2/Makefile
··· 25 obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 26 obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o 27 28 AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a 29 30 # Functions loaded to SRAM
··· 25 obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 26 obj-$(CONFIG_ARCH_OMAP4) += omap44xx-smc.o omap4-common.o 27 28 + AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a 29 AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a 30 31 # Functions loaded to SRAM
+7 -7
arch/arm/mach-omap2/clock3xxx_data.c
··· 3417 struct omap_clk *c; 3418 u32 cpu_clkflg = CK_3XXX; 3419 3420 - if (cpu_is_omap34xx()) { 3421 cpu_mask = RATE_IN_3XXX; 3422 cpu_clkflg |= CK_343X; 3423 ··· 3438 cpu_mask |= RATE_IN_3430ES2PLUS; 3439 cpu_clkflg |= CK_3430ES2; 3440 } 3441 - } else if (cpu_is_omap3517()) { 3442 - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3443 - cpu_clkflg |= CK_3517; 3444 - } else if (cpu_is_omap3505()) { 3445 - cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3446 - cpu_clkflg |= CK_3505; 3447 } 3448 3449 if (omap3_has_192mhz_clk())
··· 3417 struct omap_clk *c; 3418 u32 cpu_clkflg = CK_3XXX; 3419 3420 + if (cpu_is_omap3517()) { 3421 + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3422 + cpu_clkflg |= CK_3517; 3423 + } else if (cpu_is_omap3505()) { 3424 + cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3425 + cpu_clkflg |= CK_3505; 3426 + } else if (cpu_is_omap34xx()) { 3427 cpu_mask = RATE_IN_3XXX; 3428 cpu_clkflg |= CK_343X; 3429 ··· 3432 cpu_mask |= RATE_IN_3430ES2PLUS; 3433 cpu_clkflg |= CK_3430ES2; 3434 } 3435 } 3436 3437 if (omap3_has_192mhz_clk())
+1 -1
arch/arm/mach-omap2/id.c
··· 284 default: 285 omap_revision = OMAP3630_REV_ES1_2; 286 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 287 - break; 288 } 289 default: 290 /* Unknown default to latest silicon rev as default*/ 291 omap_revision = OMAP3630_REV_ES1_2;
··· 284 default: 285 omap_revision = OMAP3630_REV_ES1_2; 286 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 287 } 288 + break; 289 default: 290 /* Unknown default to latest silicon rev as default*/ 291 omap_revision = OMAP3630_REV_ES1_2;
+4 -2
arch/arm/mach-omap2/include/mach/entry-macro.S
··· 177 cmpne \irqnr, \tmp 178 cmpcs \irqnr, \irqnr 179 .endm 180 181 /* We assume that irqstat (the raw value of the IRQ acknowledge 182 * register) is preserved from the macro above. 183 * If there is an IPI, we immediately signal end of interrupt ··· 208 streq \irqstat, [\base, #GIC_CPU_EOI] 209 cmp \tmp, #0 210 .endm 211 - #endif 212 - #endif /* MULTI_OMAP2 */ 213 214 .macro irq_prio_table 215 .endm
··· 177 cmpne \irqnr, \tmp 178 cmpcs \irqnr, \irqnr 179 .endm 180 + #endif 181 + #endif /* MULTI_OMAP2 */ 182 183 + #ifdef CONFIG_SMP 184 /* We assume that irqstat (the raw value of the IRQ acknowledge 185 * register) is preserved from the macro above. 186 * If there is an IPI, we immediately signal end of interrupt ··· 205 streq \irqstat, [\base, #GIC_CPU_EOI] 206 cmp \tmp, #0 207 .endm 208 + #endif /* CONFIG_SMP */ 209 210 .macro irq_prio_table 211 .endm
+1 -2
arch/arm/mach-omap2/omap-smp.c
··· 102 * Send a 'sev' to wake the secondary core from WFE. 103 * Drain the outstanding writes to memory 104 */ 105 - dsb(); 106 - set_event(); 107 mb(); 108 } 109
··· 102 * Send a 'sev' to wake the secondary core from WFE. 103 * Drain the outstanding writes to memory 104 */ 105 + dsb_sev(); 106 mb(); 107 } 108
+3 -1
arch/arm/mach-omap2/pm34xx.c
··· 480 } 481 482 /* Disable IO-PAD and IO-CHAIN wakeup */ 483 - if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) { 484 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 485 omap3_disable_io_chain(); 486 }
··· 480 } 481 482 /* Disable IO-PAD and IO-CHAIN wakeup */ 483 + if (omap3_has_io_wakeup() && 484 + (per_next_state < PWRDM_POWER_ON || 485 + core_next_state < PWRDM_POWER_ON)) { 486 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); 487 omap3_disable_io_chain(); 488 }
-7
arch/arm/plat-omap/include/plat/smp.h
··· 19 20 #include <asm/hardware/gic.h> 21 22 - /* 23 - * set_event() is used to wake up secondary core from wfe using sev. ROM 24 - * code puts the second core into wfe(standby). 25 - * 26 - */ 27 - #define set_event() __asm__ __volatile__ ("sev" : : : "memory") 28 - 29 /* Needed for secondary core boot */ 30 extern void omap_secondary_startup(void); 31 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
··· 19 20 #include <asm/hardware/gic.h> 21 22 /* Needed for secondary core boot */ 23 extern void omap_secondary_startup(void); 24 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);