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rtw88: pci: define a mask for TX/RX BD indexes

Add a macro TRX_BD_IDX_MASK for access the TX/RX BD indexes.

The hardware has only 12 bits for TX/RX BD indexes, we should not
initialize a TX/RX ring or access the TX/RX BD index with a length
that is larger than TRX_BD_IDX_MASK.

Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200312080852.16684-5-yhchuang@realtek.com

authored by

Yan-Hsuan Chuang and committed by
Kalle Valo a5697a65 895c096d

+23 -11
+21 -11
drivers/net/wireless/realtek/rtw88/pci.c
··· 186 186 dma_addr_t dma; 187 187 u8 *head; 188 188 189 + if (len > TRX_BD_IDX_MASK) { 190 + rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len); 191 + return -EINVAL; 192 + } 193 + 189 194 head = pci_zalloc_consistent(pdev, ring_sz, &dma); 190 195 if (!head) { 191 196 rtw_err(rtwdev, "failed to allocate tx ring\n"); ··· 263 258 int buf_sz = RTK_PCI_RX_BUF_SIZE; 264 259 int i, allocated; 265 260 int ret = 0; 261 + 262 + if (len > TRX_BD_IDX_MASK) { 263 + rtw_err(rtwdev, "len %d exceeds maximum RX entries\n", len); 264 + return -EINVAL; 265 + } 266 266 267 267 head = pci_zalloc_consistent(pdev, ring_sz, &dma); 268 268 if (!head) { ··· 415 405 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; 416 406 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; 417 407 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; 418 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len); 408 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK); 419 409 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma); 420 410 421 411 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; 422 412 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; 423 413 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; 424 414 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; 425 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len); 415 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK); 426 416 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma); 427 417 428 418 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; 429 419 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; 430 420 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; 431 421 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; 432 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len); 422 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK); 433 423 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma); 434 424 435 425 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; 436 426 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; 437 427 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; 438 428 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; 439 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len); 429 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK); 440 430 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma); 441 431 442 432 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; 443 433 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; 444 434 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; 445 435 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; 446 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len); 436 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK); 447 437 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma); 448 438 449 439 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; 450 440 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; 451 441 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; 452 442 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; 453 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len); 443 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK); 454 444 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma); 455 445 456 446 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; 457 447 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; 458 448 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; 459 449 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; 460 - rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len); 450 + rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK); 461 451 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma); 462 452 463 453 len = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.len; 464 454 dma = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.dma; 465 455 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.rp = 0; 466 456 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; 467 - rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & 0xfff); 457 + rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK); 468 458 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma); 469 459 470 460 /* reset read/write point */ ··· 753 743 if (++ring->r.wp >= ring->r.len) 754 744 ring->r.wp = 0; 755 745 bd_idx = rtw_pci_tx_queue_idx_addr[queue]; 756 - rtw_write16(rtwdev, bd_idx, ring->r.wp & 0xfff); 746 + rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK); 757 747 } else { 758 748 u32 reg_bcn_work; 759 749 ··· 831 821 bd_idx_addr = rtw_pci_tx_queue_idx_addr[hw_queue]; 832 822 bd_idx = rtw_read32(rtwdev, bd_idx_addr); 833 823 cur_rp = bd_idx >> 16; 834 - cur_rp &= 0xfff; 824 + cur_rp &= TRX_BD_IDX_MASK; 835 825 if (cur_rp >= ring->r.rp) 836 826 count = cur_rp - ring->r.rp; 837 827 else ··· 905 895 906 896 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ); 907 897 cur_wp = tmp >> 16; 908 - cur_wp &= 0xfff; 898 + cur_wp &= TRX_BD_IDX_MASK; 909 899 if (cur_wp >= ring->r.wp) 910 900 count = cur_wp - ring->r.wp; 911 901 else
+2
drivers/net/wireless/realtek/rtw88/pci.h
··· 52 52 #define RTK_PCI_TXBD_DESA_HI0Q 0x340 53 53 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338 54 54 55 + #define TRX_BD_IDX_MASK GENMASK(11, 0) 56 + 55 57 /* BCNQ is specialized for rsvd page, does not need to specify a number */ 56 58 #define RTK_PCI_TXBD_NUM_H2CQ 0x1328 57 59 #define RTK_PCI_TXBD_NUM_MGMTQ 0x380