PCI: Cache PRI and PASID bits in pci_dev

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Device drivers need to check if an IOMMU enabled ATS, PRI and PASID in
order to know when they can use the SVM API. Cache PRI and PASID bits in
the pci_dev structure, similarly to what is currently done for ATS.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

authored by

Jean-Philippe Brucker and committed by

Bjorn Helgaas 8 years ago a4f4fa68 2ea659a9

+25

2 changed files

expand all

drivers

pci

ats.c

include

linux

pci.h

+23

drivers/pci/ats.c

··· 153 153 u32 max_requests; 154 154 int pos; 155 155 156 + if (WARN_ON(pdev->pri_enabled)) 157 + return -EBUSY; 158 + 156 159 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); 157 160 if (!pos) 158 161 return -EINVAL; ··· 173 170 control |= PCI_PRI_CTRL_ENABLE; 174 171 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); 175 172 173 + pdev->pri_enabled = 1; 174 + 176 175 return 0; 177 176 } 178 177 EXPORT_SYMBOL_GPL(pci_enable_pri); ··· 190 185 u16 control; 191 186 int pos; 192 187 188 + if (WARN_ON(!pdev->pri_enabled)) 189 + return; 190 + 193 191 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); 194 192 if (!pos) 195 193 return; ··· 200 192 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); 201 193 control &= ~PCI_PRI_CTRL_ENABLE; 202 194 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); 195 + 196 + pdev->pri_enabled = 0; 203 197 } 204 198 EXPORT_SYMBOL_GPL(pci_disable_pri); 205 199 ··· 216 206 { 217 207 u16 control; 218 208 int pos; 209 + 210 + if (WARN_ON(pdev->pri_enabled)) 211 + return -EBUSY; 219 212 220 213 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); 221 214 if (!pos) ··· 252 239 u16 control, supported; 253 240 int pos; 254 241 242 + if (WARN_ON(pdev->pasid_enabled)) 243 + return -EBUSY; 244 + 255 245 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); 256 246 if (!pos) 257 247 return -EINVAL; ··· 275 259 276 260 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); 277 261 262 + pdev->pasid_enabled = 1; 263 + 278 264 return 0; 279 265 } 280 266 EXPORT_SYMBOL_GPL(pci_enable_pasid); ··· 291 273 u16 control = 0; 292 274 int pos; 293 275 276 + if (WARN_ON(!pdev->pasid_enabled)) 277 + return; 278 + 294 279 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); 295 280 if (!pos) 296 281 return; 297 282 298 283 pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control); 284 + 285 + pdev->pasid_enabled = 0; 299 286 } 300 287 EXPORT_SYMBOL_GPL(pci_disable_pasid); 301 288

include/linux/pci.h

··· 356 356 unsigned int msix_enabled:1; 357 357 unsigned int ari_enabled:1; /* ARI forwarding */ 358 358 unsigned int ats_enabled:1; /* Address Translation Service */ 359 + unsigned int pasid_enabled:1; /* Process Address Space ID */ 360 + unsigned int pri_enabled:1; /* Page Request Interface */ 359 361 unsigned int is_managed:1; 360 362 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 361 363 unsigned int state_saved:1;