tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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ARM: dts: renesas: Move enable-method to CPU nodes

According to Documentation/devicetree/bindings/arm/cpus.yaml, the
"enable-method" property should be a property of the individual CPU
nodes, and not of the parent "cpus" container node.
However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the
"cpus" node instead.

Secondary CPU bringup and CPU hot (un)plug work regardless, as
arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.

The cpuidle code does not have such a fallback, so it does not detect
the enable-method. Note that cpuidle does not support the
"renesas,apmu" enable-method yet, so for now this does not make any
difference.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be

Geert Uytterhoeven a499e40a ebc666f3

+28 -10
+4 -1
arch/arm/boot/dts/r8a7742.dtsi
··· 47 47 cpus { 48 48 #address-cells = <1>; 49 49 #size-cells = <0>; 50 - enable-method = "renesas,apmu"; 51 50 52 51 cpu0: cpu@0 { 53 52 device_type = "cpu"; ··· 55 56 clock-frequency = <1400000000>; 56 57 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 57 58 power-domains = <&sysc R8A7742_PD_CA15_CPU0>; 59 + enable-method = "renesas,apmu"; 58 60 next-level-cache = <&L2_CA15>; 59 61 capacity-dmips-mhz = <1024>; 60 62 voltage-tolerance = <1>; /* 1% */ ··· 77 77 clock-frequency = <1400000000>; 78 78 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 79 79 power-domains = <&sysc R8A7742_PD_CA15_CPU1>; 80 + enable-method = "renesas,apmu"; 80 81 next-level-cache = <&L2_CA15>; 81 82 capacity-dmips-mhz = <1024>; 82 83 voltage-tolerance = <1>; /* 1% */ ··· 99 98 clock-frequency = <1400000000>; 100 99 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 101 100 power-domains = <&sysc R8A7742_PD_CA15_CPU2>; 101 + enable-method = "renesas,apmu"; 102 102 next-level-cache = <&L2_CA15>; 103 103 capacity-dmips-mhz = <1024>; 104 104 voltage-tolerance = <1>; /* 1% */ ··· 121 119 clock-frequency = <1400000000>; 122 120 clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; 123 121 power-domains = <&sysc R8A7742_PD_CA15_CPU3>; 122 + enable-method = "renesas,apmu"; 124 123 next-level-cache = <&L2_CA15>; 125 124 capacity-dmips-mhz = <1024>; 126 125 voltage-tolerance = <1>; /* 1% */
+2 -1
arch/arm/boot/dts/r8a7743.dtsi
··· 49 49 cpus { 50 50 #address-cells = <1>; 51 51 #size-cells = <0>; 52 - enable-method = "renesas,apmu"; 53 52 54 53 cpu0: cpu@0 { 55 54 device_type = "cpu"; ··· 58 59 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; 59 60 clock-latency = <300000>; /* 300 us */ 60 61 power-domains = <&sysc R8A7743_PD_CA15_CPU0>; 62 + enable-method = "renesas,apmu"; 61 63 next-level-cache = <&L2_CA15>; 62 64 63 65 /* kHz - uV - OPPs unknown yet */ ··· 78 78 clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; 79 79 clock-latency = <300000>; /* 300 us */ 80 80 power-domains = <&sysc R8A7743_PD_CA15_CPU1>; 81 + enable-method = "renesas,apmu"; 81 82 next-level-cache = <&L2_CA15>; 82 83 83 84 /* kHz - uV - OPPs unknown yet */
+2 -1
arch/arm/boot/dts/r8a7744.dtsi
··· 49 49 cpus { 50 50 #address-cells = <1>; 51 51 #size-cells = <0>; 52 - enable-method = "renesas,apmu"; 53 52 54 53 cpu0: cpu@0 { 55 54 device_type = "cpu"; ··· 58 59 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; 59 60 clock-latency = <300000>; /* 300 us */ 60 61 power-domains = <&sysc R8A7744_PD_CA15_CPU0>; 62 + enable-method = "renesas,apmu"; 61 63 next-level-cache = <&L2_CA15>; 62 64 63 65 /* kHz - uV - OPPs unknown yet */ ··· 78 78 clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; 79 79 clock-latency = <300000>; /* 300 us */ 80 80 power-domains = <&sysc R8A7744_PD_CA15_CPU1>; 81 + enable-method = "renesas,apmu"; 81 82 next-level-cache = <&L2_CA15>; 82 83 83 84 /* kHz - uV - OPPs unknown yet */
+2 -1
arch/arm/boot/dts/r8a7745.dtsi
··· 64 64 cpus { 65 65 #address-cells = <1>; 66 66 #size-cells = <0>; 67 - enable-method = "renesas,apmu"; 68 67 69 68 cpu0: cpu@0 { 70 69 device_type = "cpu"; ··· 72 73 clock-frequency = <1000000000>; 73 74 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; 74 75 power-domains = <&sysc R8A7745_PD_CA7_CPU0>; 76 + enable-method = "renesas,apmu"; 75 77 next-level-cache = <&L2_CA7>; 76 78 }; 77 79 ··· 83 83 clock-frequency = <1000000000>; 84 84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; 85 85 power-domains = <&sysc R8A7745_PD_CA7_CPU1>; 86 + enable-method = "renesas,apmu"; 86 87 next-level-cache = <&L2_CA7>; 87 88 }; 88 89
+2 -1
arch/arm/boot/dts/r8a77470.dtsi
··· 25 25 cpus { 26 26 #address-cells = <1>; 27 27 #size-cells = <0>; 28 - enable-method = "renesas,apmu"; 29 28 30 29 cpu0: cpu@0 { 31 30 device_type = "cpu"; ··· 33 34 clock-frequency = <1000000000>; 34 35 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 35 36 power-domains = <&sysc R8A77470_PD_CA7_CPU0>; 37 + enable-method = "renesas,apmu"; 36 38 next-level-cache = <&L2_CA7>; 37 39 }; 38 40 ··· 44 44 clock-frequency = <1000000000>; 45 45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; 46 46 power-domains = <&sysc R8A77470_PD_CA7_CPU1>; 47 + enable-method = "renesas,apmu"; 47 48 next-level-cache = <&L2_CA7>; 48 49 }; 49 50
+8 -1
arch/arm/boot/dts/r8a7790.dtsi
··· 69 69 cpus { 70 70 #address-cells = <1>; 71 71 #size-cells = <0>; 72 - enable-method = "renesas,apmu"; 73 72 74 73 cpu0: cpu@0 { 75 74 device_type = "cpu"; ··· 77 78 clock-frequency = <1300000000>; 78 79 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; 79 80 power-domains = <&sysc R8A7790_PD_CA15_CPU0>; 81 + enable-method = "renesas,apmu"; 80 82 next-level-cache = <&L2_CA15>; 81 83 capacity-dmips-mhz = <1024>; 82 84 voltage-tolerance = <1>; /* 1% */ ··· 99 99 clock-frequency = <1300000000>; 100 100 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; 101 101 power-domains = <&sysc R8A7790_PD_CA15_CPU1>; 102 + enable-method = "renesas,apmu"; 102 103 next-level-cache = <&L2_CA15>; 103 104 capacity-dmips-mhz = <1024>; 104 105 voltage-tolerance = <1>; /* 1% */ ··· 121 120 clock-frequency = <1300000000>; 122 121 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; 123 122 power-domains = <&sysc R8A7790_PD_CA15_CPU2>; 123 + enable-method = "renesas,apmu"; 124 124 next-level-cache = <&L2_CA15>; 125 125 capacity-dmips-mhz = <1024>; 126 126 voltage-tolerance = <1>; /* 1% */ ··· 143 141 clock-frequency = <1300000000>; 144 142 clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; 145 143 power-domains = <&sysc R8A7790_PD_CA15_CPU3>; 144 + enable-method = "renesas,apmu"; 146 145 next-level-cache = <&L2_CA15>; 147 146 capacity-dmips-mhz = <1024>; 148 147 voltage-tolerance = <1>; /* 1% */ ··· 165 162 clock-frequency = <780000000>; 166 163 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; 167 164 power-domains = <&sysc R8A7790_PD_CA7_CPU0>; 165 + enable-method = "renesas,apmu"; 168 166 next-level-cache = <&L2_CA7>; 169 167 capacity-dmips-mhz = <539>; 170 168 }; ··· 177 173 clock-frequency = <780000000>; 178 174 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; 179 175 power-domains = <&sysc R8A7790_PD_CA7_CPU1>; 176 + enable-method = "renesas,apmu"; 180 177 next-level-cache = <&L2_CA7>; 181 178 capacity-dmips-mhz = <539>; 182 179 }; ··· 189 184 clock-frequency = <780000000>; 190 185 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; 191 186 power-domains = <&sysc R8A7790_PD_CA7_CPU2>; 187 + enable-method = "renesas,apmu"; 192 188 next-level-cache = <&L2_CA7>; 193 189 capacity-dmips-mhz = <539>; 194 190 }; ··· 201 195 clock-frequency = <780000000>; 202 196 clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; 203 197 power-domains = <&sysc R8A7790_PD_CA7_CPU3>; 198 + enable-method = "renesas,apmu"; 204 199 next-level-cache = <&L2_CA7>; 205 200 capacity-dmips-mhz = <539>; 206 201 };
+2 -1
arch/arm/boot/dts/r8a7791.dtsi
··· 68 68 cpus { 69 69 #address-cells = <1>; 70 70 #size-cells = <0>; 71 - enable-method = "renesas,apmu"; 72 71 73 72 cpu0: cpu@0 { 74 73 device_type = "cpu"; ··· 76 77 clock-frequency = <1500000000>; 77 78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; 78 79 power-domains = <&sysc R8A7791_PD_CA15_CPU0>; 80 + enable-method = "renesas,apmu"; 79 81 next-level-cache = <&L2_CA15>; 80 82 voltage-tolerance = <1>; /* 1% */ 81 83 clock-latency = <300000>; /* 300 us */ ··· 97 97 clock-frequency = <1500000000>; 98 98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; 99 99 power-domains = <&sysc R8A7791_PD_CA15_CPU1>; 100 + enable-method = "renesas,apmu"; 100 101 next-level-cache = <&L2_CA15>; 101 102 voltage-tolerance = <1>; /* 1% */ 102 103 clock-latency = <300000>; /* 300 us */
+2 -1
arch/arm/boot/dts/r8a7792.dtsi
··· 45 45 cpus { 46 46 #address-cells = <1>; 47 47 #size-cells = <0>; 48 - enable-method = "renesas,apmu"; 49 48 50 49 cpu0: cpu@0 { 51 50 device_type = "cpu"; ··· 53 54 clock-frequency = <1000000000>; 54 55 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 55 56 power-domains = <&sysc R8A7792_PD_CA15_CPU0>; 57 + enable-method = "renesas,apmu"; 56 58 next-level-cache = <&L2_CA15>; 57 59 }; 58 60 ··· 64 64 clock-frequency = <1000000000>; 65 65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; 66 66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>; 67 + enable-method = "renesas,apmu"; 67 68 next-level-cache = <&L2_CA15>; 68 69 }; 69 70
+2 -1
arch/arm/boot/dts/r8a7793.dtsi
··· 60 60 cpus { 61 61 #address-cells = <1>; 62 62 #size-cells = <0>; 63 - enable-method = "renesas,apmu"; 64 63 65 64 cpu0: cpu@0 { 66 65 device_type = "cpu"; ··· 68 69 clock-frequency = <1500000000>; 69 70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 70 71 power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 72 + enable-method = "renesas,apmu"; 71 73 voltage-tolerance = <1>; /* 1% */ 72 74 clock-latency = <300000>; /* 300 us */ 73 75 ··· 89 89 clock-frequency = <1500000000>; 90 90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 91 91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 92 + enable-method = "renesas,apmu"; 92 93 voltage-tolerance = <1>; /* 1% */ 93 94 clock-latency = <300000>; /* 300 us */ 94 95
+2 -1
arch/arm/boot/dts/r8a7794.dtsi
··· 62 62 cpus { 63 63 #address-cells = <1>; 64 64 #size-cells = <0>; 65 - enable-method = "renesas,apmu"; 66 65 67 66 cpu0: cpu@0 { 68 67 device_type = "cpu"; ··· 70 71 clock-frequency = <1000000000>; 71 72 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; 72 73 power-domains = <&sysc R8A7794_PD_CA7_CPU0>; 74 + enable-method = "renesas,apmu"; 73 75 next-level-cache = <&L2_CA7>; 74 76 }; 75 77 ··· 81 81 clock-frequency = <1000000000>; 82 82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; 83 83 power-domains = <&sysc R8A7794_PD_CA7_CPU1>; 84 + enable-method = "renesas,apmu"; 84 85 next-level-cache = <&L2_CA7>; 85 86 }; 86 87