tjh.dev / kernel
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drm/amd/powerplay: update driver if file for sienna_cichlid

Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Likun Gao and committed by
Alex Deucher a486bc3c de273b73

+24 -10
+15 -6
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
··· 27 27 // *** IMPORTANT *** 28 28 // SMU TEAM: Always increment the interface version if 29 29 // any structure is changed in this file 30 - #define SMU11_DRIVER_IF_VERSION 0x33 30 + #define SMU11_DRIVER_IF_VERSION 0x34 31 31 32 32 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 5 33 33 ··· 968 968 969 969 typedef struct { 970 970 uint32_t CurrClock[PPCLK_COUNT]; 971 - uint16_t AverageGfxclkFrequency; 972 - uint16_t AverageFclkFrequency; 973 - uint16_t AverageUclkFrequency ; 971 + 972 + uint16_t AverageGfxclkFrequencyPreDs; 973 + uint16_t AverageGfxclkFrequencyPostDs; 974 + uint16_t AverageFclkFrequencyPreDs; 975 + uint16_t AverageFclkFrequencyPostDs; 976 + uint16_t AverageUclkFrequencyPreDs ; 977 + uint16_t AverageUclkFrequencyPostDs ; 978 + 979 + 974 980 uint16_t AverageGfxActivity ; 975 981 uint16_t AverageUclkActivity ; 976 982 uint8_t CurrSocVoltageOffset ; ··· 994 988 uint16_t TemperatureLiquid0 ; 995 989 uint16_t TemperatureLiquid1 ; 996 990 uint16_t TemperaturePlx ; 991 + uint16_t Padding16 ; 997 992 uint32_t ThrottlerStatus ; 998 993 999 994 uint8_t LinkDpmLevel; ··· 1013 1006 uint16_t AverageDclk0Frequency ; 1014 1007 uint16_t AverageVclk1Frequency ; 1015 1008 uint16_t AverageDclk1Frequency ; 1016 - uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1017 - uint16_t padding16_2; 1009 + uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence 1010 + uint8_t PcieRate ; 1011 + uint8_t PcieWidth ; 1012 + 1018 1013 } SmuMetrics_t; 1019 1014 1020 1015 typedef struct {
+1 -1
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
··· 30 30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36 31 31 #define SMU11_DRIVER_IF_VERSION_NV12 0x33 32 32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36 33 - #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33 33 + #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34 34 34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2 35 35 36 36 /* MP Apertures */
+8 -3
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
··· 70 70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ 71 71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) 72 72 73 + #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 74 + 73 75 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = { 74 76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), 75 77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), ··· 445 443 *value = metrics->CurrClock[PPCLK_DCEFCLK]; 446 444 break; 447 445 case METRICS_AVERAGE_GFXCLK: 448 - *value = metrics->AverageGfxclkFrequency; 446 + if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) 447 + *value = metrics->AverageGfxclkFrequencyPostDs; 448 + else 449 + *value = metrics->AverageGfxclkFrequencyPreDs; 449 450 break; 450 451 case METRICS_AVERAGE_FCLK: 451 - *value = metrics->AverageFclkFrequency; 452 + *value = metrics->AverageFclkFrequencyPostDs; 452 453 break; 453 454 case METRICS_AVERAGE_UCLK: 454 - *value = metrics->AverageUclkFrequency; 455 + *value = metrics->AverageUclkFrequencyPostDs; 455 456 break; 456 457 case METRICS_AVERAGE_GFXACTIVITY: 457 458 *value = metrics->AverageGfxActivity;