MIPS: SGI-IP27: clean up bridge access and header files

+89 -113

arch/mips/include/asm/pci/bridge.h

··· 45 45 46 46 #ifndef __ASSEMBLY__ 47 47 48 - /* 49 - * All accesses to bridge hardware registers must be done 50 - * using 32-bit loads and stores. 51 - */ 52 - typedef u32 bridgereg_t; 48 + #define ATE_V 0x01 49 + #define ATE_CO 0x02 50 + #define ATE_PREC 0x04 51 + #define ATE_PREF 0x08 52 + #define ATE_BAR 0x10 53 53 54 - typedef u64 bridge_ate_t; 54 + #define ATE_PFNSHIFT 12 55 + #define ATE_TIDSHIFT 8 56 + #define ATE_RMFSHIFT 48 55 57 56 - /* pointers to bridge ATEs 57 - * are always "pointer to volatile" 58 - */ 59 - typedef volatile bridge_ate_t *bridge_ate_p; 58 + #define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \ 59 + ((xid)<<ATE_TIDSHIFT) | \ 60 + (attr)) 61 + 62 + #define BRIDGE_INTERNAL_ATES 128 60 63 61 64 /* 62 65 * It is generally preferred that hardware registers on the bridge ··· 68 65 * Generated from Bridge spec dated 04oct95 69 66 */ 70 67 71 - typedef volatile struct bridge_s { 68 + struct bridge_regs { 72 69 /* Local Registers 0x000000-0x00FFFF */ 73 70 74 71 /* standard widget configuration 0x000000-0x000057 */ ··· 89 86 #define b_wid_tflush b_widget.w_tflush 90 87 91 88 /* bridge-specific widget configuration 0x000058-0x00007F */ 92 - bridgereg_t _pad_000058; 93 - bridgereg_t b_wid_aux_err; /* 0x00005C */ 94 - bridgereg_t _pad_000060; 95 - bridgereg_t b_wid_resp_upper; /* 0x000064 */ 96 - bridgereg_t _pad_000068; 97 - bridgereg_t b_wid_resp_lower; /* 0x00006C */ 98 - bridgereg_t _pad_000070; 99 - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ 100 - bridgereg_t _pad_000078[2]; 89 + u32 _pad_000058; 90 + u32 b_wid_aux_err; /* 0x00005C */ 91 + u32 _pad_000060; 92 + u32 b_wid_resp_upper; /* 0x000064 */ 93 + u32 _pad_000068; 94 + u32 b_wid_resp_lower; /* 0x00006C */ 95 + u32 _pad_000070; 96 + u32 b_wid_tst_pin_ctrl; /* 0x000074 */ 97 + u32 _pad_000078[2]; 101 98 102 99 /* PMU & Map 0x000080-0x00008F */ 103 - bridgereg_t _pad_000080; 104 - bridgereg_t b_dir_map; /* 0x000084 */ 105 - bridgereg_t _pad_000088[2]; 100 + u32 _pad_000080; 101 + u32 b_dir_map; /* 0x000084 */ 102 + u32 _pad_000088[2]; 106 103 107 104 /* SSRAM 0x000090-0x00009F */ 108 - bridgereg_t _pad_000090; 109 - bridgereg_t b_ram_perr; /* 0x000094 */ 110 - bridgereg_t _pad_000098[2]; 105 + u32 _pad_000090; 106 + u32 b_ram_perr; /* 0x000094 */ 107 + u32 _pad_000098[2]; 111 108 112 109 /* Arbitration 0x0000A0-0x0000AF */ 113 - bridgereg_t _pad_0000A0; 114 - bridgereg_t b_arb; /* 0x0000A4 */ 115 - bridgereg_t _pad_0000A8[2]; 110 + u32 _pad_0000A0; 111 + u32 b_arb; /* 0x0000A4 */ 112 + u32 _pad_0000A8[2]; 116 113 117 114 /* Number In A Can 0x0000B0-0x0000BF */ 118 - bridgereg_t _pad_0000B0; 119 - bridgereg_t b_nic; /* 0x0000B4 */ 120 - bridgereg_t _pad_0000B8[2]; 115 + u32 _pad_0000B0; 116 + u32 b_nic; /* 0x0000B4 */ 117 + u32 _pad_0000B8[2]; 121 118 122 119 /* PCI/GIO 0x0000C0-0x0000FF */ 123 - bridgereg_t _pad_0000C0; 124 - bridgereg_t b_bus_timeout; /* 0x0000C4 */ 120 + u32 _pad_0000C0; 121 + u32 b_bus_timeout; /* 0x0000C4 */ 125 122 #define b_pci_bus_timeout b_bus_timeout 126 123 127 - bridgereg_t _pad_0000C8; 128 - bridgereg_t b_pci_cfg; /* 0x0000CC */ 129 - bridgereg_t _pad_0000D0; 130 - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ 131 - bridgereg_t _pad_0000D8; 132 - bridgereg_t b_pci_err_lower; /* 0x0000DC */ 133 - bridgereg_t _pad_0000E0[8]; 124 + u32 _pad_0000C8; 125 + u32 b_pci_cfg; /* 0x0000CC */ 126 + u32 _pad_0000D0; 127 + u32 b_pci_err_upper; /* 0x0000D4 */ 128 + u32 _pad_0000D8; 129 + u32 b_pci_err_lower; /* 0x0000DC */ 130 + u32 _pad_0000E0[8]; 134 131 #define b_gio_err_lower b_pci_err_lower 135 132 #define b_gio_err_upper b_pci_err_upper 136 133 137 134 /* Interrupt 0x000100-0x0001FF */ 138 - bridgereg_t _pad_000100; 139 - bridgereg_t b_int_status; /* 0x000104 */ 140 - bridgereg_t _pad_000108; 141 - bridgereg_t b_int_enable; /* 0x00010C */ 142 - bridgereg_t _pad_000110; 143 - bridgereg_t b_int_rst_stat; /* 0x000114 */ 144 - bridgereg_t _pad_000118; 145 - bridgereg_t b_int_mode; /* 0x00011C */ 146 - bridgereg_t _pad_000120; 147 - bridgereg_t b_int_device; /* 0x000124 */ 148 - bridgereg_t _pad_000128; 149 - bridgereg_t b_int_host_err; /* 0x00012C */ 135 + u32 _pad_000100; 136 + u32 b_int_status; /* 0x000104 */ 137 + u32 _pad_000108; 138 + u32 b_int_enable; /* 0x00010C */ 139 + u32 _pad_000110; 140 + u32 b_int_rst_stat; /* 0x000114 */ 141 + u32 _pad_000118; 142 + u32 b_int_mode; /* 0x00011C */ 143 + u32 _pad_000120; 144 + u32 b_int_device; /* 0x000124 */ 145 + u32 _pad_000128; 146 + u32 b_int_host_err; /* 0x00012C */ 150 147 151 148 struct { 152 - bridgereg_t __pad; /* 0x0001{30,,,68} */ 153 - bridgereg_t addr; /* 0x0001{34,,,6C} */ 149 + u32 __pad; /* 0x0001{30,,,68} */ 150 + u32 addr; /* 0x0001{34,,,6C} */ 154 151 } b_int_addr[8]; /* 0x000130 */ 155 152 156 - bridgereg_t _pad_000170[36]; 153 + u32 _pad_000170[36]; 157 154 158 155 /* Device 0x000200-0x0003FF */ 159 156 struct { 160 - bridgereg_t __pad; /* 0x0002{00,,,38} */ 161 - bridgereg_t reg; /* 0x0002{04,,,3C} */ 157 + u32 __pad; /* 0x0002{00,,,38} */ 158 + u32 reg; /* 0x0002{04,,,3C} */ 162 159 } b_device[8]; /* 0x000200 */ 163 160 164 161 struct { 165 - bridgereg_t __pad; /* 0x0002{40,,,78} */ 166 - bridgereg_t reg; /* 0x0002{44,,,7C} */ 162 + u32 __pad; /* 0x0002{40,,,78} */ 163 + u32 reg; /* 0x0002{44,,,7C} */ 167 164 } b_wr_req_buf[8]; /* 0x000240 */ 168 165 169 166 struct { 170 - bridgereg_t __pad; /* 0x0002{80,,,88} */ 171 - bridgereg_t reg; /* 0x0002{84,,,8C} */ 167 + u32 __pad; /* 0x0002{80,,,88} */ 168 + u32 reg; /* 0x0002{84,,,8C} */ 172 169 } b_rrb_map[2]; /* 0x000280 */ 173 170 #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ 174 171 #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ 175 172 176 - bridgereg_t _pad_000290; 177 - bridgereg_t b_resp_status; /* 0x000294 */ 178 - bridgereg_t _pad_000298; 179 - bridgereg_t b_resp_clear; /* 0x00029C */ 173 + u32 _pad_000290; 174 + u32 b_resp_status; /* 0x000294 */ 175 + u32 _pad_000298; 176 + u32 b_resp_clear; /* 0x00029C */ 180 177 181 - bridgereg_t _pad_0002A0[24]; 178 + u32 _pad_0002A0[24]; 182 179 183 180 char _pad_000300[0x10000 - 0x000300]; 184 181 185 182 /* Internal Address Translation Entry RAM 0x010000-0x0103FF */ 186 183 union { 187 - bridge_ate_t wr; /* write-only */ 184 + u64 wr; /* write-only */ 188 185 struct { 189 - bridgereg_t _p_pad; 190 - bridgereg_t rd; /* read-only */ 186 + u32 _p_pad; 187 + u32 rd; /* read-only */ 191 188 } hi; 192 189 } b_int_ate_ram[128]; 193 190 ··· 195 192 196 193 /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */ 197 194 struct { 198 - bridgereg_t _p_pad; 199 - bridgereg_t rd; /* read-only */ 195 + u32 _p_pad; 196 + u32 rd; /* read-only */ 200 197 } b_int_ate_ram_lo[128]; 201 198 202 199 char _pad_011400[0x20000 - 0x011400]; ··· 215 212 } f[8]; 216 213 } b_type0_cfg_dev[8]; /* 0x020000 */ 217 214 218 - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ 215 + /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ 219 216 union { /* make all access sizes available. */ 220 217 u8 c[0x1000 / 1]; 221 218 u16 s[0x1000 / 2]; ··· 236 233 u8 _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ 237 234 238 235 /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ 239 - bridge_ate_t b_ext_ate_ram[0x10000]; 236 + u64 b_ext_ate_ram[0x10000]; 240 237 241 238 /* Reserved 0x100000-0x1FFFFF */ 242 239 char _pad_100000[0x200000-0x100000]; ··· 262 259 u32 l[0x400000 / 4]; /* read-only */ 263 260 u64 d[0x400000 / 8]; /* read-only */ 264 261 } b_external_flash; /* 0xC00000 */ 265 - } bridge_t; 262 + }; 266 263 267 264 /* 268 265 * Field formats for Error Command Word and Auxiliary Error Command Word 269 266 * of bridge. 270 267 */ 271 - typedef struct bridge_err_cmdword_s { 268 + struct bridge_err_cmdword { 272 269 union { 273 270 u32 cmd_word; 274 271 struct { ··· 285 282 rsvd:8; 286 283 } berr_st; 287 284 } berr_un; 288 - } bridge_err_cmdword_t; 285 + }; 289 286 290 287 #define berr_field berr_un.berr_st 291 288 #endif /* !__ASSEMBLY__ */ ··· 293 290 /* 294 291 * The values of these macros can and should be crosschecked 295 292 * regularly against the offsets of the like-named fields 296 - * within the "bridge_t" structure above. 293 + * within the bridge_regs structure above. 297 294 */ 298 295 299 296 /* Byte offset macros for Bridge internal registers */ ··· 800 797 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000 801 798 #define PCI64_ATTR_RMF_SHFT 48 802 799 803 - #ifndef __ASSEMBLY__ 804 - /* Address translation entry for mapped pci32 accesses */ 805 - typedef union ate_u { 806 - u64 ent; 807 - struct ate_s { 808 - u64 rmf:16; 809 - u64 addr:36; 810 - u64 targ:4; 811 - u64 reserved:3; 812 - u64 barrier:1; 813 - u64 prefetch:1; 814 - u64 precise:1; 815 - u64 coherent:1; 816 - u64 valid:1; 817 - } field; 818 - } ate_t; 819 - #endif /* !__ASSEMBLY__ */ 820 - 821 - #define ATE_V 0x01 822 - #define ATE_CO 0x02 823 - #define ATE_PREC 0x04 824 - #define ATE_PREF 0x08 825 - #define ATE_BAR 0x10 826 - 827 - #define ATE_PFNSHIFT 12 828 - #define ATE_TIDSHIFT 8 829 - #define ATE_RMFSHIFT 48 830 - 831 - #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \ 832 - ((xid)<<ATE_TIDSHIFT) | \ 833 - (attr) 834 - 835 - #define BRIDGE_INTERNAL_ATES 128 836 - 837 800 struct bridge_controller { 838 801 struct pci_controller pc; 839 802 struct resource mem; 840 803 struct resource io; 841 804 struct resource busn; 842 - bridge_t *base; 805 + struct bridge_regs *base; 843 806 nasid_t nasid; 844 807 unsigned int widget_id; 845 808 unsigned int irq_cpu; ··· 815 846 816 847 #define BRIDGE_CONTROLLER(bus) \ 817 848 ((struct bridge_controller *)((bus)->sysdata)) 849 + 850 + #define bridge_read(bc, reg) __raw_readl(&bc->base->reg) 851 + #define bridge_write(bc, reg, val) __raw_writel(val, &bc->base->reg) 852 + #define bridge_set(bc, reg, val) \ 853 + __raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg) 854 + #define bridge_clr(bc, reg, val) \ 855 + __raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg) 818 856 819 857 extern void register_bridge_irq(unsigned int irq); 820 858 extern int request_bridge_irq(struct bridge_controller *bc);

-5

arch/mips/include/asm/sn/sn0/addrs.h

··· 134 134 135 135 #define CALIAS_BASE CAC_BASE 136 136 137 - 138 - 139 - #define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ 140 - ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 141 - 142 137 #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) 143 138 144 139 /* Turn on sable logging for the processors whose bits are set. */

+24 -44

arch/mips/pci/ops-bridge.c

··· 44 44 int where, int size, u32 * value) 45 45 { 46 46 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 47 - bridge_t *bridge = bc->base; 47 + struct bridge_regs *bridge = bc->base; 48 48 int slot = PCI_SLOT(devfn); 49 49 int fn = PCI_FUNC(devfn); 50 50 volatile void *addr; ··· 56 56 return PCIBIOS_DEVICE_NOT_FOUND; 57 57 58 58 /* 59 - * IOC3 is fucking fucked beyond belief ... Don't even give the 59 + * IOC3 is broken beyond belief ... Don't even give the 60 60 * generic PCI code a chance to look at it for real ... 61 61 */ 62 62 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 63 - goto oh_my_gawd; 63 + goto is_ioc3; 64 64 65 65 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 66 66 ··· 73 73 74 74 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 75 75 76 - oh_my_gawd: 76 + is_ioc3: 77 77 78 78 /* 79 - * IOC3 is fucking fucked beyond belief ... Don't even give the 80 - * generic PCI code a chance to look at the wrong register. 79 + * IOC3 special handling 81 80 */ 82 81 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 83 82 *value = emulate_ioc3_cfg(where, size); 84 83 return PCIBIOS_SUCCESSFUL; 85 84 } 86 85 87 - /* 88 - * IOC3 is fucking fucked beyond belief ... Don't try to access 89 - * anything but 32-bit words ... 90 - */ 91 86 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 92 87 93 88 if (get_dbe(cf, (u32 *) addr)) ··· 99 104 int where, int size, u32 * value) 100 105 { 101 106 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 102 - bridge_t *bridge = bc->base; 107 + struct bridge_regs *bridge = bc->base; 103 108 int busno = bus->number; 104 109 int slot = PCI_SLOT(devfn); 105 110 int fn = PCI_FUNC(devfn); ··· 107 112 u32 cf, shift, mask; 108 113 int res; 109 114 110 - bridge->b_pci_cfg = (busno << 16) | (slot << 11); 115 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 111 116 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 112 117 if (get_dbe(cf, (u32 *) addr)) 113 118 return PCIBIOS_DEVICE_NOT_FOUND; 114 119 115 120 /* 116 - * IOC3 is fucking fucked beyond belief ... Don't even give the 121 + * IOC3 is broken beyond belief ... Don't even give the 117 122 * generic PCI code a chance to look at it for real ... 118 123 */ 119 124 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 120 - goto oh_my_gawd; 125 + goto is_ioc3; 121 126 122 - bridge->b_pci_cfg = (busno << 16) | (slot << 11); 127 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 123 128 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 124 129 125 130 if (size == 1) ··· 131 136 132 137 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 133 138 134 - oh_my_gawd: 139 + is_ioc3: 135 140 136 141 /* 137 - * IOC3 is fucking fucked beyond belief ... Don't even give the 138 - * generic PCI code a chance to look at the wrong register. 142 + * IOC3 special handling 139 143 */ 140 144 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { 141 145 *value = emulate_ioc3_cfg(where, size); 142 146 return PCIBIOS_SUCCESSFUL; 143 147 } 144 148 145 - /* 146 - * IOC3 is fucking fucked beyond belief ... Don't try to access 147 - * anything but 32-bit words ... 148 - */ 149 - bridge->b_pci_cfg = (busno << 16) | (slot << 11); 149 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 150 150 addr = &bridge->b_type1_cfg.c[(fn << 8) | where]; 151 151 152 152 if (get_dbe(cf, (u32 *) addr)) ··· 167 177 int where, int size, u32 value) 168 178 { 169 179 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 170 - bridge_t *bridge = bc->base; 180 + struct bridge_regs *bridge = bc->base; 171 181 int slot = PCI_SLOT(devfn); 172 182 int fn = PCI_FUNC(devfn); 173 183 volatile void *addr; ··· 179 189 return PCIBIOS_DEVICE_NOT_FOUND; 180 190 181 191 /* 182 - * IOC3 is fucking fucked beyond belief ... Don't even give the 192 + * IOC3 is broken beyond belief ... Don't even give the 183 193 * generic PCI code a chance to look at it for real ... 184 194 */ 185 195 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 186 - goto oh_my_gawd; 196 + goto is_ioc3; 187 197 188 198 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; 189 199 ··· 200 210 201 211 return PCIBIOS_SUCCESSFUL; 202 212 203 - oh_my_gawd: 213 + is_ioc3: 204 214 205 215 /* 206 - * IOC3 is fucking fucked beyond belief ... Don't even give the 207 - * generic PCI code a chance to touch the wrong register. 216 + * IOC3 special handling 208 217 */ 209 218 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 210 219 return PCIBIOS_SUCCESSFUL; 211 220 212 - /* 213 - * IOC3 is fucking fucked beyond belief ... Don't try to access 214 - * anything but 32-bit words ... 215 - */ 216 221 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 217 222 218 223 if (get_dbe(cf, (u32 *) addr)) ··· 228 243 int where, int size, u32 value) 229 244 { 230 245 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); 231 - bridge_t *bridge = bc->base; 246 + struct bridge_regs *bridge = bc->base; 232 247 int slot = PCI_SLOT(devfn); 233 248 int fn = PCI_FUNC(devfn); 234 249 int busno = bus->number; ··· 236 251 u32 cf, shift, mask, smask; 237 252 int res; 238 253 239 - bridge->b_pci_cfg = (busno << 16) | (slot << 11); 254 + bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); 240 255 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; 241 256 if (get_dbe(cf, (u32 *) addr)) 242 257 return PCIBIOS_DEVICE_NOT_FOUND; 243 258 244 259 /* 245 - * IOC3 is fucking fucked beyond belief ... Don't even give the 260 + * IOC3 is broken beyond belief ... Don't even give the 246 261 * generic PCI code a chance to look at it for real ... 247 262 */ 248 263 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) 249 - goto oh_my_gawd; 264 + goto is_ioc3; 250 265 251 266 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; 252 267 ··· 263 278 264 279 return PCIBIOS_SUCCESSFUL; 265 280 266 - oh_my_gawd: 281 + is_ioc3: 267 282 268 283 /* 269 - * IOC3 is fucking fucked beyond belief ... Don't even give the 270 - * generic PCI code a chance to touch the wrong register. 284 + * IOC3 special handling 271 285 */ 272 286 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) 273 287 return PCIBIOS_SUCCESSFUL; 274 288 275 - /* 276 - * IOC3 is fucking fucked beyond belief ... Don't try to access 277 - * anything but 32-bit words ... 278 - */ 279 289 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; 280 290 281 291 if (get_dbe(cf, (u32 *) addr))

+14 -17

arch/mips/pci/pci-ip27.c

··· 47 47 unsigned long offset = NODE_OFFSET(nasid); 48 48 struct bridge_controller *bc; 49 49 static int num_bridges = 0; 50 - bridge_t *bridge; 51 50 int slot; 52 51 53 52 pci_set_flags(PCI_PROBE_ONLY); ··· 86 87 /* 87 88 * point to this bridge 88 89 */ 89 - bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); 90 + bc->base = (struct bridge_regs *)RAW_NODE_SWIN_BASE(nasid, widget_id); 90 91 91 92 /* 92 93 * Clear all pending interrupts. 93 94 */ 94 - bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; 95 + bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR); 95 96 96 97 /* 97 98 * Until otherwise set up, assume all interrupts are from slot 0 98 99 */ 99 - bridge->b_int_device = 0x0; 100 + bridge_write(bc, b_int_device, 0x0); 100 101 101 102 /* 102 103 * swap pio's to pci mem and io space (big windows) 103 104 */ 104 - bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 105 - BRIDGE_CTRL_MEM_SWAP; 105 + bridge_set(bc, b_wid_control, BRIDGE_CTRL_IO_SWAP | 106 + BRIDGE_CTRL_MEM_SWAP); 106 107 #ifdef CONFIG_PAGE_SIZE_4KB 107 - bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; 108 + bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 108 109 #else /* 16kB or larger */ 109 - bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE; 110 + bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); 110 111 #endif 111 112 112 113 /* 113 114 * Hmm... IRIX sets additional bits in the address which 114 115 * are documented as reserved in the bridge docs. 115 116 */ 116 - bridge->b_wid_int_upper = 0x8000 | (masterwid << 16); 117 - bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/ 118 - bridge->b_dir_map = (masterwid << 20); /* DMA */ 119 - bridge->b_int_enable = 0; 117 + bridge_write(bc, b_wid_int_upper, 0x8000 | (masterwid << 16)); 118 + bridge_write(bc, b_wid_int_lower, 0x01800090); /* PI_INT_PEND_MOD off*/ 119 + bridge_write(bc, b_dir_map, (masterwid << 20)); /* DMA */ 120 + bridge_write(bc, b_int_enable, 0); 120 121 121 122 for (slot = 0; slot < 8; slot ++) { 122 - bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 123 + bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); 123 124 bc->pci_int[slot] = -1; 124 125 } 125 - bridge->b_wid_tflush; /* wait until Bridge PIO complete */ 126 - 127 - bc->base = bridge; 126 + bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */ 128 127 129 128 register_pci_controller(&bc->pc); 130 129 ··· 203 206 static inline void pci_disable_swapping(struct pci_dev *dev) 204 207 { 205 208 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); 206 - bridge_t *bridge = bc->base; 209 + struct bridge_regs *bridge = bc->base; 207 210 int slot = PCI_SLOT(dev->devfn); 208 211 209 212 /* Turn off byte swapping */

+11 -13

arch/mips/sgi-ip27/ip27-irq-pci.c

··· 136 136 static unsigned int startup_bridge_irq(struct irq_data *d) 137 137 { 138 138 struct bridge_controller *bc; 139 - bridgereg_t device; 140 - bridge_t *bridge; 141 139 int pin, swlevel; 142 140 cpuid_t cpu; 141 + u64 device; 143 142 144 143 pin = SLOT_FROM_PCI_IRQ(d->irq); 145 144 bc = IRQ_TO_BRIDGE(d->irq); 146 - bridge = bc->base; 147 145 148 146 pr_debug("bridge_startup(): irq= 0x%x pin=%d\n", d->irq, pin); 149 147 /* ··· 149 151 * of INT_PEND0 are taken 150 152 */ 151 153 swlevel = find_level(&cpu, d->irq); 152 - bridge->b_int_addr[pin].addr = (0x20000 | swlevel | (bc->nasid << 8)); 153 - bridge->b_int_enable |= (1 << pin); 154 - bridge->b_int_enable |= 0x7ffffe00; /* more stuff in int_enable */ 154 + bridge_write(bc, b_int_addr[pin].addr, 155 + (0x20000 | swlevel | (bc->nasid << 8))); 156 + bridge_set(bc, b_int_enable, (1 << pin)); 157 + bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ 155 158 156 159 /* 157 160 * Enable sending of an interrupt clear packt to the hub on a high to ··· 161 162 * IRIX sets additional bits in the address which are documented as 162 163 * reserved in the bridge docs. 163 164 */ 164 - bridge->b_int_mode |= (1UL << pin); 165 + bridge_set(bc, b_int_mode, (1UL << pin)); 165 166 166 167 /* 167 168 * We assume the bridge to have a 1:1 mapping between devices 168 169 * (slots) and intr pins. 169 170 */ 170 - device = bridge->b_int_device; 171 + device = bridge_read(bc, b_int_device); 171 172 device &= ~(7 << (pin*3)); 172 173 device |= (pin << (pin*3)); 173 - bridge->b_int_device = device; 174 + bridge_write(bc, b_int_device, device); 174 175 175 - bridge->b_wid_tflush; 176 + bridge_read(bc, b_wid_tflush); 176 177 177 178 intr_connect_level(cpu, swlevel); 178 179 ··· 183 184 static void shutdown_bridge_irq(struct irq_data *d) 184 185 { 185 186 struct bridge_controller *bc = IRQ_TO_BRIDGE(d->irq); 186 - bridge_t *bridge = bc->base; 187 187 int pin, swlevel; 188 188 cpuid_t cpu; 189 189 ··· 196 198 swlevel = find_level(&cpu, d->irq); 197 199 intr_disconnect_level(cpu, swlevel); 198 200 199 - bridge->b_int_enable &= ~(1 << pin); 200 - bridge->b_wid_tflush; 201 + bridge_clr(bc, b_int_enable, (1 << pin)); 202 + bridge_read(bc, b_wid_tflush); 201 203 } 202 204 203 205 static inline void enable_bridge_irq(struct irq_data *d)