Merge tag 'gic-fixes-for-4.9-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull GIC updates from Marc Zyngier:

- Fix for 32bit accesses that should be 64bit on 64bit machines
- Fix for a field decoding macro
- Beautify a warning message

Changed files
+7 -7
drivers
include
linux
irqchip
+5 -5
drivers/irqchip/irq-gic-v3-its.c
··· 1023 1023 1024 1024 static int its_alloc_tables(struct its_node *its) 1025 1025 { 1026 - u64 typer = readq_relaxed(its->base + GITS_TYPER); 1026 + u64 typer = gic_read_typer(its->base + GITS_TYPER); 1027 1027 u32 ids = GITS_TYPER_DEVBITS(typer); 1028 1028 u64 shr = GITS_BASER_InnerShareable; 1029 1029 u64 cache = GITS_BASER_WaWb; ··· 1198 1198 * We now have to bind each collection to its target 1199 1199 * redistributor. 1200 1200 */ 1201 - if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 1201 + if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { 1202 1202 /* 1203 1203 * This ITS wants the physical address of the 1204 1204 * redistributor. ··· 1208 1208 /* 1209 1209 * This ITS wants a linear CPU number. 1210 1210 */ 1211 - target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER); 1211 + target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); 1212 1212 target = GICR_TYPER_CPU_NUMBER(target) << 16; 1213 1213 } 1214 1214 ··· 1691 1691 INIT_LIST_HEAD(&its->its_device_list); 1692 1692 its->base = its_base; 1693 1693 its->phys_base = res->start; 1694 - its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1694 + its->ite_size = ((gic_read_typer(its_base + GITS_TYPER) >> 4) & 0xf) + 1; 1695 1695 its->numa_node = numa_node; 1696 1696 1697 1697 its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL); ··· 1763 1763 1764 1764 static bool gic_rdists_supports_plpis(void) 1765 1765 { 1766 - return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 1766 + return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); 1767 1767 } 1768 1768 1769 1769 int its_cpu_init(void)
+1 -1
drivers/irqchip/irq-gic.c
··· 1279 1279 */ 1280 1280 *base += 0xf000; 1281 1281 cpuif_res.start += 0xf000; 1282 - pr_warn("GIC: Adjusting CPU interface base to %pa", 1282 + pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1283 1283 &cpuif_res.start); 1284 1284 } 1285 1285
+1 -1
include/linux/irqchip/arm-gic-v3.h
··· 290 290 #define GITS_BASER_TYPE_SHIFT (56) 291 291 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) 292 292 #define GITS_BASER_ENTRY_SIZE_SHIFT (48) 293 - #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0xff) + 1) 293 + #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) 294 294 #define GITS_BASER_SHAREABILITY_SHIFT (10) 295 295 #define GITS_BASER_InnerShareable \ 296 296 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)