Merge tag 'tegra-for-5.20-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

-1

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

··· 40 40 - compatible 41 41 - reg 42 42 - nvidia,bpmp 43 - - status 44 43 45 44 examples: 46 45 - |

+40

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: NVIDIA Tegra194 AXI2APB bridge 8 + 9 + maintainers: 10 + - Sumit Gupta <sumitg@nvidia.com> 11 + 12 + properties: 13 + $nodename: 14 + pattern: "^axi2apb@([0-9a-f]+)$" 15 + 16 + compatible: 17 + enum: 18 + - nvidia,tegra194-axi2apb 19 + 20 + reg: 21 + maxItems: 6 22 + description: Physical base address and length of registers for all bridges 23 + 24 + additionalProperties: false 25 + 26 + required: 27 + - compatible 28 + - reg 29 + 30 + examples: 31 + - | 32 + axi2apb: axi2apb@2390000 { 33 + compatible = "nvidia,tegra194-axi2apb"; 34 + reg = <0x02390000 0x1000>, 35 + <0x023a0000 0x1000>, 36 + <0x023b0000 0x1000>, 37 + <0x023c0000 0x1000>, 38 + <0x023d0000 0x1000>, 39 + <0x023e0000 0x1000>; 40 + };

+97

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: NVIDIA Tegra194 CBB 1.0 bindings 8 + 9 + maintainers: 10 + - Sumit Gupta <sumitg@nvidia.com> 11 + 12 + description: |+ 13 + The Control Backbone (CBB) is comprised of the physical path from an 14 + initiator to a target's register configuration space. CBB 1.0 has 15 + multiple hierarchical sub-NOCs (Network-on-Chip) and connects various 16 + initiators and targets using different bridges like AXIP2P, AXI2APB. 17 + 18 + This driver handles errors due to illegal register accesses reported 19 + by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs 20 + "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC" 21 + which is the main NOC. 22 + 23 + By default, the access issuing initiator is informed about the error 24 + using SError or Data Abort exception unless the ERD (Error Response 25 + Disable) is enabled/set for that initiator. If the ERD is enabled, then 26 + SError or Data Abort is masked and the error is reported with interrupt. 27 + 28 + - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the 29 + errors due to illegal accesses from CCPLEX are reported by interrupts. 30 + If ERD is not set, then error is reported by SError. 31 + - For other initiators, the ERD is disabled. So, the access issuing 32 + initiator is informed about the illegal access by Data Abort exception. 33 + In addition, an interrupt is also generated to CCPLEX. These initiators 34 + include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and 35 + engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder 36 + engine) etc which can initiate transactions. 37 + 38 + The driver prints relevant debug information like Error Code, Error 39 + Description, Master, Address, AXI ID, Cache, Protection, Security Group 40 + etc on receiving error notification. 41 + 42 + properties: 43 + $nodename: 44 + pattern: "^[a-z]+-noc@[0-9a-f]+$" 45 + 46 + compatible: 47 + enum: 48 + - nvidia,tegra194-cbb-noc 49 + - nvidia,tegra194-aon-noc 50 + - nvidia,tegra194-bpmp-noc 51 + - nvidia,tegra194-rce-noc 52 + - nvidia,tegra194-sce-noc 53 + 54 + reg: 55 + maxItems: 1 56 + 57 + interrupts: 58 + description: 59 + CCPLEX receives secure or nonsecure interrupt depending on error type. 60 + A secure interrupt is received for SEC(firewall) & SLV errors and a 61 + non-secure interrupt is received for TMO & DEC errors. 62 + items: 63 + - description: non-secure interrupt 64 + - description: secure interrupt 65 + 66 + nvidia,axi2apb: 67 + $ref: '/schemas/types.yaml#/definitions/phandle' 68 + description: 69 + Specifies the node having all axi2apb bridges which need to be checked 70 + for any error logged in their status register. 71 + 72 + nvidia,apbmisc: 73 + $ref: '/schemas/types.yaml#/definitions/phandle' 74 + description: 75 + Specifies the apbmisc node which need to be used for reading the ERD 76 + register. 77 + 78 + additionalProperties: false 79 + 80 + required: 81 + - compatible 82 + - reg 83 + - interrupts 84 + - nvidia,apbmisc 85 + 86 + examples: 87 + - | 88 + #include <dt-bindings/interrupt-controller/arm-gic.h> 89 + 90 + cbb-noc@2300000 { 91 + compatible = "nvidia,tegra194-cbb-noc"; 92 + reg = <0x02300000 0x1000>; 93 + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 94 + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 95 + nvidia,axi2apb = <&axi2apb>; 96 + nvidia,apbmisc = <&apbmisc>; 97 + };

+74

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: NVIDIA Tegra CBB 2.0 bindings 8 + 9 + maintainers: 10 + - Sumit Gupta <sumitg@nvidia.com> 11 + 12 + description: |+ 13 + The Control Backbone (CBB) is comprised of the physical path from an 14 + initiator to a target's register configuration space. CBB 2.0 consists 15 + of multiple sub-blocks connected to each other to create a topology. 16 + The Tegra234 SoC has different fabrics based on CBB 2.0 architecture 17 + which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and 18 + "CBB central fabric". 19 + 20 + In CBB 2.0, each initiator which can issue transactions connects to a 21 + Root Master Node (MN) before it connects to any other element of the 22 + fabric. Each Root MN contains a Error Monitor (EM) which detects and 23 + logs error. Interrupts from various EM blocks are collated by Error 24 + Notifier (EN) which is per fabric and presents a single interrupt from 25 + fabric to the SoC interrupt controller. 26 + 27 + The driver handles errors from CBB due to illegal register accesses 28 + and prints debug information about failed transaction on receiving 29 + the interrupt from EN. Debug information includes Error Code, Error 30 + Description, MasterID, Fabric, SlaveID, Address, Cache, Protection, 31 + Security Group etc on receiving error notification. 32 + 33 + If the Error Response Disable (ERD) is set/enabled for an initiator, 34 + then SError or Data abort exception error response is masked and an 35 + interrupt is used for reporting errors due to illegal accesses from 36 + that initiator. The value returned on read failures is '0xFFFFFFFF' 37 + for compatibility with PCIE. 38 + 39 + properties: 40 + $nodename: 41 + pattern: "^[a-z]+-fabric@[0-9a-f]+$" 42 + 43 + compatible: 44 + enum: 45 + - nvidia,tegra234-aon-fabric 46 + - nvidia,tegra234-bpmp-fabric 47 + - nvidia,tegra234-cbb-fabric 48 + - nvidia,tegra234-dce-fabric 49 + - nvidia,tegra234-rce-fabric 50 + - nvidia,tegra234-sce-fabric 51 + 52 + reg: 53 + maxItems: 1 54 + 55 + interrupts: 56 + items: 57 + - description: secure interrupt from error notifier 58 + 59 + additionalProperties: false 60 + 61 + required: 62 + - compatible 63 + - reg 64 + - interrupts 65 + 66 + examples: 67 + - | 68 + #include <dt-bindings/interrupt-controller/arm-gic.h> 69 + 70 + cbb-fabric@1300000 { 71 + compatible = "nvidia,tegra234-cbb-fabric"; 72 + reg = <0x13a00000 0x400000>; 73 + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 74 + };

+109

Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 + 7 + title: NVIDIA Tegra186 timer 8 + 9 + maintainers: 10 + - Thierry Reding <treding@nvidia.com> 11 + 12 + description: > 13 + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp 14 + counter. Each NV timer selects its timing reference signal from the 1 MHz 15 + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be 16 + programmed to generate one-shot, periodic, or watchdog interrupts. 17 + 18 + 19 + properties: 20 + compatible: 21 + oneOf: 22 + - const: nvidia,tegra186-timer 23 + description: > 24 + The Tegra186 timer provides ten 29-bit timer counters. 25 + - const: nvidia,tegra234-timer 26 + description: > 27 + The Tegra234 timer provides sixteen 29-bit timer counters. 28 + 29 + reg: 30 + maxItems: 1 31 + 32 + interrupts: true 33 + 34 + allOf: 35 + - if: 36 + properties: 37 + compatible: 38 + contains: 39 + const: nvidia,tegra186-timer 40 + then: 41 + properties: 42 + interrupts: 43 + maxItems: 10 44 + description: > 45 + One per each timer channels 0 through 9. 46 + 47 + - if: 48 + properties: 49 + compatible: 50 + contains: 51 + const: nvidia,tegra234-timer 52 + then: 53 + properties: 54 + interrupts: 55 + maxItems: 16 56 + description: > 57 + One per each timer channels 0 through 15. 58 + 59 + required: 60 + - compatible 61 + - reg 62 + - interrupts 63 + 64 + additionalProperties: false 65 + 66 + examples: 67 + - | 68 + #include <dt-bindings/interrupt-controller/arm-gic.h> 69 + #include <dt-bindings/interrupt-controller/irq.h> 70 + 71 + timer@3010000 { 72 + compatible = "nvidia,tegra186-timer"; 73 + reg = <0x03010000 0x000e0000>; 74 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 75 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 76 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 77 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 78 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 79 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 80 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 81 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 82 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 83 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 84 + }; 85 + 86 + - | 87 + #include <dt-bindings/interrupt-controller/arm-gic.h> 88 + #include <dt-bindings/interrupt-controller/irq.h> 89 + 90 + timer@2080000 { 91 + compatible = "nvidia,tegra234-timer"; 92 + reg = <0x02080000 0x00121000>; 93 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 94 + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 95 + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 96 + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 97 + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 98 + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 99 + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 100 + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 101 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 102 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 103 + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 104 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 105 + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 106 + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 107 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 108 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 109 + };

+105

include/dt-bindings/clock/tegra234-clock.h

··· 38 38 * throughput and memory controller power. 39 39 */ 40 40 #define TEGRA234_CLK_EMC 31U 41 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 42 + #define TEGRA234_CLK_HOST1X 46U 41 43 /** @brief output of gate CLK_ENB_FUSE */ 42 44 #define TEGRA234_CLK_FUSE 40U 43 45 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ ··· 134 132 #define TEGRA234_CLK_UARTA 155U 135 133 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 136 134 #define TEGRA234_CLK_PEX1_C6_CORE 161U 135 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 136 + #define TEGRA234_CLK_VIC 167U 137 137 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 138 138 #define TEGRA234_CLK_PEX2_C7_CORE 171U 139 139 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ ··· 168 164 #define TEGRA234_CLK_PEX1_C5_CORE 225U 169 165 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 170 166 #define TEGRA234_CLK_PLLC4 237U 167 + /** @brief RX clock recovered from MGBE0 lane input */ 168 + #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 169 + /** @brief RX clock recovered from MGBE1 lane input */ 170 + #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 171 + /** @brief RX clock recovered from MGBE2 lane input */ 172 + #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 173 + /** @brief RX clock recovered from MGBE3 lane input */ 174 + #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 171 175 /** @brief 32K input clock provided by PMIC */ 172 176 #define TEGRA234_CLK_CLK_32K 289U 177 + /** @brief Monitored branch of MBGE0 RX input clock */ 178 + #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 179 + /** @brief Monitored branch of MBGE1 RX input clock */ 180 + #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 181 + /** @brief Monitored branch of MBGE2 RX input clock */ 182 + #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 183 + /** @brief Monitored branch of MBGE3 RX input clock */ 184 + #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 185 + /** @brief Monitored branch of MGBE0 RX PCS mux output */ 186 + #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 187 + /** @brief Monitored branch of MGBE1 RX PCS mux output */ 188 + #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 189 + /** @brief Monitored branch of MGBE2 RX PCS mux output */ 190 + #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 191 + /** @brief Monitored branch of MGBE3 RX PCS mux output */ 192 + #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 193 + /** @brief RX PCS clock recovered from MGBE0 lane input */ 194 + #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 195 + /** @brief RX PCS clock recovered from MGBE1 lane input */ 196 + #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 197 + /** @brief RX PCS clock recovered from MGBE2 lane input */ 198 + #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 199 + /** @brief RX PCS clock recovered from MGBE3 lane input */ 200 + #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 201 + /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 202 + #define TEGRA234_CLK_MGBE0_RX_PCS 373U 203 + /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 204 + #define TEGRA234_CLK_MGBE0_TX 374U 205 + /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 206 + #define TEGRA234_CLK_MGBE0_TX_PCS 375U 207 + /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 208 + #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 209 + /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 210 + #define TEGRA234_CLK_MGBE0_MAC 377U 211 + /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 212 + #define TEGRA234_CLK_MGBE0_MACSEC 378U 213 + /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 214 + #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 215 + /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 216 + #define TEGRA234_CLK_MGBE0_APP 380U 217 + /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 218 + #define TEGRA234_CLK_MGBE0_PTP_REF 381U 219 + /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 220 + #define TEGRA234_CLK_MGBE1_RX_PCS 382U 221 + /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 222 + #define TEGRA234_CLK_MGBE1_TX 383U 223 + /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 224 + #define TEGRA234_CLK_MGBE1_TX_PCS 384U 225 + /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 226 + #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 227 + /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 228 + #define TEGRA234_CLK_MGBE1_MAC 386U 229 + /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 230 + #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 231 + /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 232 + #define TEGRA234_CLK_MGBE1_APP 389U 233 + /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 234 + #define TEGRA234_CLK_MGBE1_PTP_REF 390U 235 + /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 236 + #define TEGRA234_CLK_MGBE2_RX_PCS 391U 237 + /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 238 + #define TEGRA234_CLK_MGBE2_TX 392U 239 + /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 240 + #define TEGRA234_CLK_MGBE2_TX_PCS 393U 241 + /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 242 + #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 243 + /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 244 + #define TEGRA234_CLK_MGBE2_MAC 395U 245 + /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 246 + #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 247 + /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 248 + #define TEGRA234_CLK_MGBE2_APP 398U 249 + /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 250 + #define TEGRA234_CLK_MGBE2_PTP_REF 399U 251 + /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 252 + #define TEGRA234_CLK_MGBE3_RX_PCS 400U 253 + /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 254 + #define TEGRA234_CLK_MGBE3_TX 401U 255 + /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 256 + #define TEGRA234_CLK_MGBE3_TX_PCS 402U 257 + /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 258 + #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 259 + /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 260 + #define TEGRA234_CLK_MGBE3_MAC 404U 261 + /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 262 + #define TEGRA234_CLK_MGBE3_MACSEC 405U 263 + /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 264 + #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 265 + /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 266 + #define TEGRA234_CLK_MGBE3_APP 407U 267 + /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 268 + #define TEGRA234_CLK_MGBE3_PTP_REF 408U 173 269 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 174 270 #define TEGRA234_CLK_AZA_2XBIT 457U 175 271 /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 176 272 #define TEGRA234_CLK_AZA_BIT 458U 273 + 177 274 #endif

+26

include/dt-bindings/memory/tegra234-mc.h

··· 11 11 /* NISO0 stream IDs */ 12 12 #define TEGRA234_SID_APE 0x02 13 13 #define TEGRA234_SID_HDA 0x03 14 + #define TEGRA234_SID_GPCDMA 0x04 15 + #define TEGRA234_SID_MGBE 0x06 14 16 #define TEGRA234_SID_PCIE0 0x12 15 17 #define TEGRA234_SID_PCIE4 0x13 16 18 #define TEGRA234_SID_PCIE5 0x14 17 19 #define TEGRA234_SID_PCIE6 0x15 18 20 #define TEGRA234_SID_PCIE9 0x1f 21 + #define TEGRA234_SID_MGBE_VF1 0x49 22 + #define TEGRA234_SID_MGBE_VF2 0x4a 23 + #define TEGRA234_SID_MGBE_VF3 0x4b 19 24 20 25 /* NISO1 stream IDs */ 21 26 #define TEGRA234_SID_SDMMC4 0x02 ··· 31 26 #define TEGRA234_SID_PCIE8 0x09 32 27 #define TEGRA234_SID_PCIE10 0x0b 33 28 #define TEGRA234_SID_BPMP 0x10 29 + #define TEGRA234_SID_HOST1X 0x27 30 + #define TEGRA234_SID_VIC 0x34 34 31 35 32 /* 36 33 * memory client IDs ··· 40 33 41 34 /* High-definition audio (HDA) read clients */ 42 35 #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 36 + #define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 43 37 /* PCIE6 read clients */ 44 38 #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 45 39 /* PCIE6 write clients */ ··· 69 61 #define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 70 62 /* PCIE7r1 read clients */ 71 63 #define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 64 + /* MGBE0 read client */ 65 + #define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58 66 + /* MGBEB read client */ 67 + #define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59 68 + /* MGBEC read client */ 69 + #define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a 70 + /* MGBED read client */ 71 + #define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b 72 + /* MGBE0 write client */ 73 + #define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c 74 + /* MGBEB write client */ 75 + #define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f 76 + /* MGBEC write client */ 77 + #define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61 72 78 /* sdmmcd memory read client */ 73 79 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 80 + /* MGBED write client */ 81 + #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 74 82 /* sdmmcd memory write client */ 75 83 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 84 + #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 85 + #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 76 86 /* BPMP read client */ 77 87 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 78 88 /* BPMP write client */

+2

include/dt-bindings/power/tegra234-powergate.h

··· 18 18 #define TEGRA234_POWER_DOMAIN_MGBEA 17U 19 19 #define TEGRA234_POWER_DOMAIN_MGBEB 18U 20 20 #define TEGRA234_POWER_DOMAIN_MGBEC 19U 21 + #define TEGRA234_POWER_DOMAIN_MGBED 20U 22 + #define TEGRA234_POWER_DOMAIN_VIC 29U 21 23 22 24 #endif

+10

include/dt-bindings/reset/tegra234-reset.h

··· 15 15 #define TEGRA234_RESET_PEX1_COMMON_APB 13U 16 16 #define TEGRA234_RESET_PEX2_CORE_7 14U 17 17 #define TEGRA234_RESET_PEX2_CORE_7_APB 15U 18 + #define TEGRA234_RESET_GPCDMA 18U 18 19 #define TEGRA234_RESET_HDA 20U 19 20 #define TEGRA234_RESET_HDACODEC 21U 20 21 #define TEGRA234_RESET_I2C1 24U ··· 30 29 #define TEGRA234_RESET_I2C7 33U 31 30 #define TEGRA234_RESET_I2C8 34U 32 31 #define TEGRA234_RESET_I2C9 35U 32 + #define TEGRA234_RESET_MGBE0_PCS 45U 33 + #define TEGRA234_RESET_MGBE0_MAC 46U 34 + #define TEGRA234_RESET_MGBE1_PCS 49U 35 + #define TEGRA234_RESET_MGBE1_MAC 50U 36 + #define TEGRA234_RESET_MGBE2_PCS 53U 37 + #define TEGRA234_RESET_MGBE2_MAC 54U 33 38 #define TEGRA234_RESET_PEX2_CORE_10 56U 34 39 #define TEGRA234_RESET_PEX2_CORE_10_APB 57U 35 40 #define TEGRA234_RESET_PEX2_COMMON_APB 58U ··· 50 43 #define TEGRA234_RESET_QSPI0 76U 51 44 #define TEGRA234_RESET_QSPI1 77U 52 45 #define TEGRA234_RESET_SDMMC4 85U 46 + #define TEGRA234_RESET_MGBE3_PCS 87U 47 + #define TEGRA234_RESET_MGBE3_MAC 88U 53 48 #define TEGRA234_RESET_UARTA 100U 49 + #define TEGRA234_RESET_VIC 113U 54 50 #define TEGRA234_RESET_PEX0_CORE_0 116U 55 51 #define TEGRA234_RESET_PEX0_CORE_1 117U 56 52 #define TEGRA234_RESET_PEX0_CORE_2 118U