tjh.dev / kernel
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Merge tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt

Merge "STi DT changes for v4.4, round 2" from Maxime Coquelin:

- Use STiH418's A9 PLL
- Add Ethernet support to STiH407 family

* tag 'sti-dt-for-v4.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
ARM: STi: DT: Add support for stih418 A9 pll
ARM: dts: Enable Ethernet on STi's B2199 board
ARM: dts: Enable Ethernet on STi's B2120 boards
ARM: dts: Add Ethernet node to STiH407 family
ARM: dts: Fix RGMII pinctrl timings

Arnd Bergmann a3de778b 7007c60c

+46 -3
+1
arch/arm/boot/dts/stih407-b2120.dts
··· 25 25 26 26 aliases { 27 27 ttyAS0 = &sbc_serial0; 28 + ethernet0 = &ethernet0; 28 29 }; 29 30 30 31 };
+27
arch/arm/boot/dts/stih407-family.dtsi
··· 653 653 clocks = <&clk_sysin>; 654 654 status = "okay"; 655 655 }; 656 + 657 + ethernet0: dwmac@9630000 { 658 + device_type = "network"; 659 + status = "disabled"; 660 + compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 661 + reg = <0x9630000 0x8000>, <0x80 0x4>; 662 + reg-names = "stmmaceth", "sti-ethconf"; 663 + 664 + st,syscon = <&syscfg_sbc_reg 0x80>; 665 + st,gmac_en; 666 + resets = <&softreset STIH407_ETH1_SOFTRESET>; 667 + reset-names = "stmmaceth"; 668 + 669 + interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 670 + <GIC_SPI 99 IRQ_TYPE_NONE>; 671 + interrupt-names = "macirq", "eth_wake_irq"; 672 + 673 + /* DMA Bus Mode */ 674 + snps,pbl = <8>; 675 + 676 + pinctrl-names = "default"; 677 + pinctrl-0 = <&pinctrl_rgmii1>; 678 + 679 + clock-names = "stmmaceth", "sti-ethclk"; 680 + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 681 + <&clk_s_c0_flexgen CLK_ETH_PHY>; 682 + }; 656 683 }; 657 684 };
+2 -2
arch/arm/boot/dts/stih407-pinctrl.dtsi
··· 216 216 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; 217 217 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; 218 218 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>; 219 - rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>; 219 + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; 220 220 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>; 221 - phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>; 221 + phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>; 222 222 }; 223 223 }; 224 224
+1
arch/arm/boot/dts/stih410-b2120.dts
··· 25 25 26 26 aliases { 27 27 ttyAS0 = &sbc_serial0; 28 + ethernet0 = &ethernet0; 28 29 }; 29 30 30 31 soc {
+8
arch/arm/boot/dts/stih418-b2199.dts
··· 24 24 25 25 aliases { 26 26 ttyAS0 = &sbc_serial0; 27 + ethernet0 = &ethernet0; 27 28 }; 28 29 29 30 soc { ··· 101 100 102 101 st_dwc3: dwc3@8f94000 { 103 102 status = "okay"; 103 + }; 104 + 105 + ethernet0: dwmac@9630000 { 106 + st,tx-retime-src = "clkgen"; 107 + status = "okay"; 108 + phy-mode = "rgmii"; 109 + fixed-link = <0 1 1000 0 0>; 104 110 }; 105 111 }; 106 112 };
+1 -1
arch/arm/boot/dts/stih418-clock.dtsi
··· 44 44 45 45 clockgen_a9_pll: clockgen-a9-pll { 46 46 #clock-cells = <1>; 47 - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; 47 + compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; 48 48 49 49 clocks = <&clk_sysin>; 50 50
+6
arch/arm/boot/dts/stihxxx-b2120.dtsi
··· 87 87 status = "okay"; 88 88 }; 89 89 90 + ethernet0: dwmac@9630000 { 91 + st,tx-retime-src = "clkgen"; 92 + status = "okay"; 93 + phy-mode = "rgmii"; 94 + fixed-link = <0 1 1000 0 0>; 95 + }; 90 96 }; 91 97 };