tjh.dev / kernel
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drm: radeon: *_cs_packet_parse_vline() cleanup

Simplify the way the return value is set a number of times (mostly on
error).

Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

authored by

Paul Bolle and committed by
Dave Airlie a3a88a66 3409fc1b

+23 -42
unified split
+8 -16
drivers/gpu/drm/radeon/evergreen_cs.c
··· 293 293 if (wait_reg_mem.type != PACKET_TYPE3 || 294 294 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 295 295 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 296 - r = -EINVAL; 297 - return r; 296 + return -EINVAL; 298 297 } 299 298 300 299 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 301 300 /* bit 4 is reg (0) or mem (1) */ 302 301 if (wait_reg_mem_info & 0x10) { 303 302 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 304 - r = -EINVAL; 305 - return r; 303 + return -EINVAL; 306 304 } 307 305 /* waiting for value to be equal */ 308 306 if ((wait_reg_mem_info & 0x7) != 0x3) { 309 307 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 310 - r = -EINVAL; 311 - return r; 308 + return -EINVAL; 312 309 } 313 310 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) { 314 311 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 315 - r = -EINVAL; 316 - return r; 312 + return -EINVAL; 317 313 } 318 314 319 315 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) { 320 316 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 321 - r = -EINVAL; 322 - return r; 317 + return -EINVAL; 323 318 } 324 319 325 320 /* jump over the NOP */ ··· 332 337 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 333 338 if (!obj) { 334 339 DRM_ERROR("cannot find crtc %d\n", crtc_id); 335 - r = -EINVAL; 336 - goto out; 340 + return -EINVAL; 337 341 } 338 342 crtc = obj_to_crtc(obj); 339 343 radeon_crtc = to_radeon_crtc(crtc); ··· 357 363 break; 358 364 default: 359 365 DRM_ERROR("unknown crtc reloc\n"); 360 - r = -EINVAL; 361 - goto out; 366 + return -EINVAL; 362 367 } 363 368 } 364 - out: 365 - return r; 369 + return 0; 366 370 } 367 371 368 372 static int evergreen_packet0_check(struct radeon_cs_parser *p,
+6 -10
drivers/gpu/drm/radeon/r100.c
··· 1205 1205 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1206 1206 waitreloc.count != 0) { 1207 1207 DRM_ERROR("vline wait had illegal wait until segment\n"); 1208 - r = -EINVAL; 1209 - return r; 1208 + return -EINVAL; 1210 1209 } 1211 1210 1212 1211 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1213 1212 DRM_ERROR("vline wait had illegal wait until\n"); 1214 - r = -EINVAL; 1215 - return r; 1213 + return -EINVAL; 1216 1214 } 1217 1215 1218 1216 /* jump over the NOP */ ··· 1228 1230 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1229 1231 if (!obj) { 1230 1232 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1231 - r = -EINVAL; 1232 - goto out; 1233 + return -EINVAL; 1233 1234 } 1234 1235 crtc = obj_to_crtc(obj); 1235 1236 radeon_crtc = to_radeon_crtc(crtc); ··· 1250 1253 break; 1251 1254 default: 1252 1255 DRM_ERROR("unknown crtc reloc\n"); 1253 - r = -EINVAL; 1254 - goto out; 1256 + return -EINVAL; 1255 1257 } 1256 1258 ib[h_idx] = header; 1257 1259 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1258 1260 } 1259 - out: 1260 - return r; 1261 + 1262 + return 0; 1261 1263 } 1262 1264 1263 1265 /**
+9 -16
drivers/gpu/drm/radeon/r600_cs.c
··· 780 780 if (wait_reg_mem.type != PACKET_TYPE3 || 781 781 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 782 782 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 783 - r = -EINVAL; 784 - return r; 783 + return -EINVAL; 785 784 } 786 785 787 786 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 788 787 /* bit 4 is reg (0) or mem (1) */ 789 788 if (wait_reg_mem_info & 0x10) { 790 789 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 791 - r = -EINVAL; 792 - return r; 790 + return -EINVAL; 793 791 } 794 792 /* waiting for value to be equal */ 795 793 if ((wait_reg_mem_info & 0x7) != 0x3) { 796 794 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 797 - r = -EINVAL; 798 - return r; 795 + return -EINVAL; 799 796 } 800 797 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { 801 798 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 802 - r = -EINVAL; 803 - return r; 799 + return -EINVAL; 804 800 } 805 801 806 802 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { 807 803 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 808 - r = -EINVAL; 809 - return r; 804 + return -EINVAL; 810 805 } 811 806 812 807 /* jump over the NOP */ ··· 820 825 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 821 826 if (!obj) { 822 827 DRM_ERROR("cannot find crtc %d\n", crtc_id); 823 - r = -EINVAL; 824 - goto out; 828 + return -EINVAL; 825 829 } 826 830 crtc = obj_to_crtc(obj); 827 831 radeon_crtc = to_radeon_crtc(crtc); ··· 843 849 break; 844 850 default: 845 851 DRM_ERROR("unknown crtc reloc\n"); 846 - r = -EINVAL; 847 - goto out; 852 + return -EINVAL; 848 853 } 849 854 ib[h_idx] = header; 850 855 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; 851 856 } 852 - out: 853 - return r; 857 + 858 + return 0; 854 859 } 855 860 856 861 static int r600_packet0_check(struct radeon_cs_parser *p,