Merge remote-tracking branches 'asoc/topic/atmel', 'asoc/topic/bcm2835' and 'asoc/topic/cs42xx8' into asoc-next

+1

drivers/misc/atmel-ssc.c

··· 34 34 if (ssc->pdev->dev.of_node) { 35 35 if (of_alias_get_id(ssc->pdev->dev.of_node, "ssc") 36 36 == ssc_num) { 37 + ssc->pdev->id = ssc_num; 37 38 ssc_valid = 1; 38 39 break; 39 40 }

+18 -9

sound/soc/atmel/atmel_ssc_dai.c

··· 285 285 static int atmel_ssc_startup(struct snd_pcm_substream *substream, 286 286 struct snd_soc_dai *dai) 287 287 { 288 - struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 288 + struct platform_device *pdev = to_platform_device(dai->dev); 289 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 289 290 struct atmel_pcm_dma_params *dma_params; 290 291 int dir, dir_mask; 291 292 int ret; ··· 347 346 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream, 348 347 struct snd_soc_dai *dai) 349 348 { 350 - struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 349 + struct platform_device *pdev = to_platform_device(dai->dev); 350 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 351 351 struct atmel_pcm_dma_params *dma_params; 352 352 int dir, dir_mask; 353 353 ··· 394 392 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai, 395 393 unsigned int fmt) 396 394 { 397 - struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 395 + struct platform_device *pdev = to_platform_device(cpu_dai->dev); 396 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 398 397 399 398 ssc_p->daifmt = fmt; 400 399 return 0; ··· 407 404 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 408 405 int div_id, int div) 409 406 { 410 - struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id]; 407 + struct platform_device *pdev = to_platform_device(cpu_dai->dev); 408 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 411 409 412 410 switch (div_id) { 413 411 case ATMEL_SSC_CMR_DIV: ··· 449 445 struct snd_pcm_hw_params *params, 450 446 struct snd_soc_dai *dai) 451 447 { 452 - int id = dai->id; 448 + struct platform_device *pdev = to_platform_device(dai->dev); 449 + int id = pdev->id; 453 450 struct atmel_ssc_info *ssc_p = &ssc_info[id]; 454 451 struct ssc_device *ssc = ssc_p->ssc; 455 452 struct atmel_pcm_dma_params *dma_params; ··· 777 772 static int atmel_ssc_prepare(struct snd_pcm_substream *substream, 778 773 struct snd_soc_dai *dai) 779 774 { 780 - struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 775 + struct platform_device *pdev = to_platform_device(dai->dev); 776 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 781 777 struct atmel_pcm_dma_params *dma_params; 782 778 int dir; 783 779 ··· 801 795 static int atmel_ssc_trigger(struct snd_pcm_substream *substream, 802 796 int cmd, struct snd_soc_dai *dai) 803 797 { 804 - struct atmel_ssc_info *ssc_p = &ssc_info[dai->id]; 798 + struct platform_device *pdev = to_platform_device(dai->dev); 799 + struct atmel_ssc_info *ssc_p = &ssc_info[pdev->id]; 805 800 struct atmel_pcm_dma_params *dma_params; 806 801 int dir; 807 802 ··· 831 824 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai) 832 825 { 833 826 struct atmel_ssc_info *ssc_p; 827 + struct platform_device *pdev = to_platform_device(cpu_dai->dev); 834 828 835 829 if (!cpu_dai->active) 836 830 return 0; 837 831 838 - ssc_p = &ssc_info[cpu_dai->id]; 832 + ssc_p = &ssc_info[pdev->id]; 839 833 840 834 /* Save the status register before disabling transmit and receive */ 841 835 ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR); ··· 860 852 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai) 861 853 { 862 854 struct atmel_ssc_info *ssc_p; 855 + struct platform_device *pdev = to_platform_device(cpu_dai->dev); 863 856 u32 cr; 864 857 865 858 if (!cpu_dai->active) 866 859 return 0; 867 860 868 - ssc_p = &ssc_info[cpu_dai->id]; 861 + ssc_p = &ssc_info[pdev->id]; 869 862 870 863 /* restore SSC register settings */ 871 864 ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);

+64 -220

sound/soc/bcm/bcm2835-i2s.c

··· 37 37 #include <linux/init.h> 38 38 #include <linux/io.h> 39 39 #include <linux/module.h> 40 + #include <linux/of_address.h> 40 41 #include <linux/slab.h> 41 42 42 43 #include <sound/core.h> ··· 46 45 #include <sound/pcm.h> 47 46 #include <sound/pcm_params.h> 48 47 #include <sound/soc.h> 49 - 50 - /* Clock registers */ 51 - #define BCM2835_CLK_PCMCTL_REG 0x00 52 - #define BCM2835_CLK_PCMDIV_REG 0x04 53 - 54 - /* Clock register settings */ 55 - #define BCM2835_CLK_PASSWD (0x5a000000) 56 - #define BCM2835_CLK_PASSWD_MASK (0xff000000) 57 - #define BCM2835_CLK_MASH(v) ((v) << 9) 58 - #define BCM2835_CLK_FLIP BIT(8) 59 - #define BCM2835_CLK_BUSY BIT(7) 60 - #define BCM2835_CLK_KILL BIT(5) 61 - #define BCM2835_CLK_ENAB BIT(4) 62 - #define BCM2835_CLK_SRC(v) (v) 63 - 64 - #define BCM2835_CLK_SHIFT (12) 65 - #define BCM2835_CLK_DIVI(v) ((v) << BCM2835_CLK_SHIFT) 66 - #define BCM2835_CLK_DIVF(v) (v) 67 - #define BCM2835_CLK_DIVF_MASK (0xFFF) 68 - 69 - enum { 70 - BCM2835_CLK_MASH_0 = 0, 71 - BCM2835_CLK_MASH_1, 72 - BCM2835_CLK_MASH_2, 73 - BCM2835_CLK_MASH_3, 74 - }; 75 - 76 - enum { 77 - BCM2835_CLK_SRC_GND = 0, 78 - BCM2835_CLK_SRC_OSC, 79 - BCM2835_CLK_SRC_DBG0, 80 - BCM2835_CLK_SRC_DBG1, 81 - BCM2835_CLK_SRC_PLLA, 82 - BCM2835_CLK_SRC_PLLC, 83 - BCM2835_CLK_SRC_PLLD, 84 - BCM2835_CLK_SRC_HDMI, 85 - }; 86 - 87 - /* Most clocks are not useable (freq = 0) */ 88 - static const unsigned int bcm2835_clk_freq[BCM2835_CLK_SRC_HDMI+1] = { 89 - [BCM2835_CLK_SRC_GND] = 0, 90 - [BCM2835_CLK_SRC_OSC] = 19200000, 91 - [BCM2835_CLK_SRC_DBG0] = 0, 92 - [BCM2835_CLK_SRC_DBG1] = 0, 93 - [BCM2835_CLK_SRC_PLLA] = 0, 94 - [BCM2835_CLK_SRC_PLLC] = 0, 95 - [BCM2835_CLK_SRC_PLLD] = 500000000, 96 - [BCM2835_CLK_SRC_HDMI] = 0, 97 - }; 98 48 99 49 /* I2S registers */ 100 50 #define BCM2835_I2S_CS_A_REG 0x00 ··· 110 158 #define BCM2835_I2S_INT_RXR BIT(1) 111 159 #define BCM2835_I2S_INT_TXW BIT(0) 112 160 113 - /* I2S DMA interface */ 114 - /* FIXME: Needs IOMMU support */ 115 - #define BCM2835_VCMMU_SHIFT (0x7E000000 - 0x20000000) 116 - 117 161 /* General device struct */ 118 162 struct bcm2835_i2s_dev { 119 163 struct device *dev; ··· 117 169 unsigned int fmt; 118 170 unsigned int bclk_ratio; 119 171 120 - struct regmap *i2s_regmap; 121 - struct regmap *clk_regmap; 172 + struct regmap *i2s_regmap; 173 + struct clk *clk; 174 + bool clk_prepared; 122 175 }; 123 176 124 177 static void bcm2835_i2s_start_clock(struct bcm2835_i2s_dev *dev) 125 178 { 126 - /* Start the clock if in master mode */ 127 179 unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; 180 + 181 + if (dev->clk_prepared) 182 + return; 128 183 129 184 switch (master) { 130 185 case SND_SOC_DAIFMT_CBS_CFS: 131 186 case SND_SOC_DAIFMT_CBS_CFM: 132 - regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, 133 - BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB, 134 - BCM2835_CLK_PASSWD | BCM2835_CLK_ENAB); 187 + clk_prepare_enable(dev->clk); 188 + dev->clk_prepared = true; 135 189 break; 136 190 default: 137 191 break; ··· 142 192 143 193 static void bcm2835_i2s_stop_clock(struct bcm2835_i2s_dev *dev) 144 194 { 145 - uint32_t clkreg; 146 - int timeout = 1000; 147 - 148 - /* Stop clock */ 149 - regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, 150 - BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB, 151 - BCM2835_CLK_PASSWD); 152 - 153 - /* Wait for the BUSY flag going down */ 154 - while (--timeout) { 155 - regmap_read(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, &clkreg); 156 - if (!(clkreg & BCM2835_CLK_BUSY)) 157 - break; 158 - } 159 - 160 - if (!timeout) { 161 - /* KILL the clock */ 162 - dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n"); 163 - regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, 164 - BCM2835_CLK_KILL | BCM2835_CLK_PASSWD_MASK, 165 - BCM2835_CLK_KILL | BCM2835_CLK_PASSWD); 166 - } 195 + if (dev->clk_prepared) 196 + clk_disable_unprepare(dev->clk); 197 + dev->clk_prepared = false; 167 198 } 168 199 169 200 static void bcm2835_i2s_clear_fifos(struct bcm2835_i2s_dev *dev, ··· 154 223 uint32_t syncval; 155 224 uint32_t csreg; 156 225 uint32_t i2s_active_state; 157 - uint32_t clkreg; 158 - uint32_t clk_active_state; 226 + bool clk_was_prepared; 159 227 uint32_t off; 160 228 uint32_t clr; 161 229 ··· 168 238 regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); 169 239 i2s_active_state = csreg & (BCM2835_I2S_RXON | BCM2835_I2S_TXON); 170 240 171 - regmap_read(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, &clkreg); 172 - clk_active_state = clkreg & BCM2835_CLK_ENAB; 173 - 174 241 /* Start clock if not running */ 175 - if (!clk_active_state) { 176 - regmap_update_bits(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, 177 - BCM2835_CLK_PASSWD_MASK | BCM2835_CLK_ENAB, 178 - BCM2835_CLK_PASSWD | BCM2835_CLK_ENAB); 179 - } 242 + clk_was_prepared = dev->clk_prepared; 243 + if (!clk_was_prepared) 244 + bcm2835_i2s_start_clock(dev); 180 245 181 246 /* Stop I2S module */ 182 247 regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, off, 0); ··· 205 280 dev_err(dev->dev, "I2S SYNC error!\n"); 206 281 207 282 /* Stop clock if it was not running before */ 208 - if (!clk_active_state) 283 + if (!clk_was_prepared) 209 284 bcm2835_i2s_stop_clock(dev); 210 285 211 286 /* Restore I2S state */ ··· 234 309 struct snd_soc_dai *dai) 235 310 { 236 311 struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 237 - 238 312 unsigned int sampling_rate = params_rate(params); 239 313 unsigned int data_length, data_delay, bclk_ratio; 240 314 unsigned int ch1pos, ch2pos, mode, format; 241 - unsigned int mash = BCM2835_CLK_MASH_1; 242 - unsigned int divi, divf, target_frequency; 243 - int clk_src = -1; 244 - unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; 245 - bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS 246 - || master == SND_SOC_DAIFMT_CBS_CFM); 247 - 248 - bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS 249 - || master == SND_SOC_DAIFMT_CBM_CFS); 250 315 uint32_t csreg; 251 316 252 317 /* ··· 258 343 switch (params_format(params)) { 259 344 case SNDRV_PCM_FORMAT_S16_LE: 260 345 data_length = 16; 261 - bclk_ratio = 40; 262 346 break; 263 347 case SNDRV_PCM_FORMAT_S32_LE: 264 348 data_length = 32; 265 - bclk_ratio = 80; 266 349 break; 267 350 default: 268 351 return -EINVAL; ··· 269 356 /* If bclk_ratio already set, use that one. */ 270 357 if (dev->bclk_ratio) 271 358 bclk_ratio = dev->bclk_ratio; 359 + else 360 + /* otherwise calculate a fitting block ratio */ 361 + bclk_ratio = 2 * data_length; 272 362 273 - /* 274 - * Clock Settings 275 - * 276 - * The target frequency of the bit clock is 277 - * sampling rate * frame length 278 - * 279 - * Integer mode: 280 - * Sampling rates that are multiples of 8000 kHz 281 - * can be driven by the oscillator of 19.2 MHz 282 - * with an integer divider as long as the frame length 283 - * is an integer divider of 19200000/8000=2400 as set up above. 284 - * This is no longer possible if the sampling rate 285 - * is too high (e.g. 192 kHz), because the oscillator is too slow. 286 - * 287 - * MASH mode: 288 - * For all other sampling rates, it is not possible to 289 - * have an integer divider. Approximate the clock 290 - * with the MASH module that induces a slight frequency 291 - * variance. To minimize that it is best to have the fastest 292 - * clock here. That is PLLD with 500 MHz. 293 - */ 294 - target_frequency = sampling_rate * bclk_ratio; 295 - clk_src = BCM2835_CLK_SRC_OSC; 296 - mash = BCM2835_CLK_MASH_0; 297 - 298 - if (bcm2835_clk_freq[clk_src] % target_frequency == 0 299 - && bit_master && frame_master) { 300 - divi = bcm2835_clk_freq[clk_src] / target_frequency; 301 - divf = 0; 302 - } else { 303 - uint64_t dividend; 304 - 305 - if (!dev->bclk_ratio) { 306 - /* 307 - * Overwrite bclk_ratio, because the 308 - * above trick is not needed or can 309 - * not be used. 310 - */ 311 - bclk_ratio = 2 * data_length; 312 - } 313 - 314 - target_frequency = sampling_rate * bclk_ratio; 315 - 316 - clk_src = BCM2835_CLK_SRC_PLLD; 317 - mash = BCM2835_CLK_MASH_1; 318 - 319 - dividend = bcm2835_clk_freq[clk_src]; 320 - dividend <<= BCM2835_CLK_SHIFT; 321 - do_div(dividend, target_frequency); 322 - divi = dividend >> BCM2835_CLK_SHIFT; 323 - divf = dividend & BCM2835_CLK_DIVF_MASK; 324 - } 325 - 326 - /* Set clock divider */ 327 - regmap_write(dev->clk_regmap, BCM2835_CLK_PCMDIV_REG, BCM2835_CLK_PASSWD 328 - | BCM2835_CLK_DIVI(divi) 329 - | BCM2835_CLK_DIVF(divf)); 330 - 331 - /* Setup clock, but don't start it yet */ 332 - regmap_write(dev->clk_regmap, BCM2835_CLK_PCMCTL_REG, BCM2835_CLK_PASSWD 333 - | BCM2835_CLK_MASH(mash) 334 - | BCM2835_CLK_SRC(clk_src)); 363 + /* set target clock rate*/ 364 + clk_set_rate(dev->clk, sampling_rate * bclk_ratio); 335 365 336 366 /* Setup the frame format */ 337 367 format = BCM2835_I2S_CHEN; ··· 548 692 .trigger = bcm2835_i2s_trigger, 549 693 .hw_params = bcm2835_i2s_hw_params, 550 694 .set_fmt = bcm2835_i2s_set_dai_fmt, 551 - .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio 695 + .set_bclk_ratio = bcm2835_i2s_set_dai_bclk_ratio, 552 696 }; 553 697 554 698 static int bcm2835_i2s_dai_probe(struct snd_soc_dai *dai) ··· 606 750 }; 607 751 } 608 752 609 - static bool bcm2835_clk_volatile_reg(struct device *dev, unsigned int reg) 610 - { 611 - switch (reg) { 612 - case BCM2835_CLK_PCMCTL_REG: 613 - return true; 614 - default: 615 - return false; 616 - }; 617 - } 618 - 619 - static const struct regmap_config bcm2835_regmap_config[] = { 620 - { 621 - .reg_bits = 32, 622 - .reg_stride = 4, 623 - .val_bits = 32, 624 - .max_register = BCM2835_I2S_GRAY_REG, 625 - .precious_reg = bcm2835_i2s_precious_reg, 626 - .volatile_reg = bcm2835_i2s_volatile_reg, 627 - .cache_type = REGCACHE_RBTREE, 628 - }, 629 - { 630 - .reg_bits = 32, 631 - .reg_stride = 4, 632 - .val_bits = 32, 633 - .max_register = BCM2835_CLK_PCMDIV_REG, 634 - .volatile_reg = bcm2835_clk_volatile_reg, 635 - .cache_type = REGCACHE_RBTREE, 636 - }, 753 + static const struct regmap_config bcm2835_regmap_config = { 754 + .reg_bits = 32, 755 + .reg_stride = 4, 756 + .val_bits = 32, 757 + .max_register = BCM2835_I2S_GRAY_REG, 758 + .precious_reg = bcm2835_i2s_precious_reg, 759 + .volatile_reg = bcm2835_i2s_volatile_reg, 760 + .cache_type = REGCACHE_RBTREE, 637 761 }; 638 762 639 763 static const struct snd_soc_component_driver bcm2835_i2s_component = { ··· 623 787 static int bcm2835_i2s_probe(struct platform_device *pdev) 624 788 { 625 789 struct bcm2835_i2s_dev *dev; 626 - int i; 627 790 int ret; 628 - struct regmap *regmap[2]; 629 - struct resource *mem[2]; 630 - 631 - /* Request both ioareas */ 632 - for (i = 0; i <= 1; i++) { 633 - void __iomem *base; 634 - 635 - mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); 636 - base = devm_ioremap_resource(&pdev->dev, mem[i]); 637 - if (IS_ERR(base)) 638 - return PTR_ERR(base); 639 - 640 - regmap[i] = devm_regmap_init_mmio(&pdev->dev, base, 641 - &bcm2835_regmap_config[i]); 642 - if (IS_ERR(regmap[i])) 643 - return PTR_ERR(regmap[i]); 644 - } 791 + struct resource *mem; 792 + void __iomem *base; 793 + const __be32 *addr; 794 + dma_addr_t dma_base; 645 795 646 796 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), 647 797 GFP_KERNEL); 648 798 if (!dev) 649 799 return -ENOMEM; 650 800 651 - dev->i2s_regmap = regmap[0]; 652 - dev->clk_regmap = regmap[1]; 801 + /* get the clock */ 802 + dev->clk_prepared = false; 803 + dev->clk = devm_clk_get(&pdev->dev, NULL); 804 + if (IS_ERR(dev->clk)) { 805 + dev_err(&pdev->dev, "could not get clk: %ld\n", 806 + PTR_ERR(dev->clk)); 807 + return PTR_ERR(dev->clk); 808 + } 653 809 654 - /* Set the DMA address */ 810 + /* Request ioarea */ 811 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 812 + base = devm_ioremap_resource(&pdev->dev, mem); 813 + if (IS_ERR(base)) 814 + return PTR_ERR(base); 815 + 816 + dev->i2s_regmap = devm_regmap_init_mmio(&pdev->dev, base, 817 + &bcm2835_regmap_config); 818 + if (IS_ERR(dev->i2s_regmap)) 819 + return PTR_ERR(dev->i2s_regmap); 820 + 821 + /* Set the DMA address - we have to parse DT ourselves */ 822 + addr = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 823 + if (!addr) { 824 + dev_err(&pdev->dev, "could not get DMA-register address\n"); 825 + return -EINVAL; 826 + } 827 + dma_base = be32_to_cpup(addr); 828 + 655 829 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = 656 - (dma_addr_t)mem[0]->start + BCM2835_I2S_FIFO_A_REG 657 - + BCM2835_VCMMU_SHIFT; 830 + dma_base + BCM2835_I2S_FIFO_A_REG; 658 831 659 832 dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = 660 - (dma_addr_t)mem[0]->start + BCM2835_I2S_FIFO_A_REG 661 - + BCM2835_VCMMU_SHIFT; 833 + dma_base + BCM2835_I2S_FIFO_A_REG; 662 834 663 835 /* Set the bus width */ 664 836 dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width =

+8 -2

sound/soc/codecs/cs42xx8.c

··· 44 44 45 45 bool slave_mode; 46 46 unsigned long sysclk; 47 + u32 tx_channels; 47 48 }; 48 49 49 50 /* -127.5dB to 0dB with step of 0.5dB */ ··· 258 257 u32 ratio = cs42xx8->sysclk / params_rate(params); 259 258 u32 i, fm, val, mask; 260 259 260 + if (tx) 261 + cs42xx8->tx_channels = params_channels(params); 262 + 261 263 for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) { 262 264 if (cs42xx8_ratios[i].ratio == ratio) 263 265 break; ··· 287 283 { 288 284 struct snd_soc_codec *codec = dai->codec; 289 285 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec); 286 + u8 dac_unmute = cs42xx8->tx_channels ? 287 + ~((0x1 << cs42xx8->tx_channels) - 1) : 0; 290 288 291 - regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE, 292 - CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0); 289 + regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, 290 + mute ? CS42XX8_DACMUTE_ALL : dac_unmute); 293 291 294 292 return 0; 295 293 }