tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amd/display: Add CRC and DMUB test support

[Why & How]
- Add CRC for test support
- Add params to allow control into to DMUB.

Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Charlene Liu and committed by
Alex Deucher a36f7254 a8b53760

+32
+29
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
··· 161 161 uint32_t OTG_CRC_CNTL2; 162 162 uint32_t OTG_CRC0_DATA_RG; 163 163 uint32_t OTG_CRC0_DATA_B; 164 + uint32_t OTG_CRC1_DATA_B; 165 + uint32_t OTG_CRC2_DATA_B; 166 + uint32_t OTG_CRC3_DATA_B; 167 + uint32_t OTG_CRC1_DATA_RG; 168 + uint32_t OTG_CRC2_DATA_RG; 169 + uint32_t OTG_CRC3_DATA_RG; 164 170 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; 165 171 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; 166 172 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; 167 173 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; 174 + uint32_t OTG_CRC1_WINDOWA_X_CONTROL; 175 + uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; 176 + uint32_t OTG_CRC1_WINDOWB_X_CONTROL; 177 + uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; 168 178 uint32_t GSL_SOURCE_SELECT; 169 179 uint32_t DWB_SOURCE_SELECT; 170 180 uint32_t OTG_DSC_START_POSITION; ··· 474 464 type CRC0_R_CR;\ 475 465 type CRC0_G_Y;\ 476 466 type CRC0_B_CB;\ 467 + type CRC1_R_CR;\ 468 + type CRC1_G_Y;\ 469 + type CRC1_B_CB;\ 470 + type CRC2_R_CR;\ 471 + type CRC2_G_Y;\ 472 + type CRC2_B_CB;\ 473 + type CRC3_R_CR;\ 474 + type CRC3_G_Y;\ 475 + type CRC3_B_CB;\ 477 476 type OTG_CRC0_WINDOWA_X_START;\ 478 477 type OTG_CRC0_WINDOWA_X_END;\ 479 478 type OTG_CRC0_WINDOWA_Y_START;\ ··· 491 472 type OTG_CRC0_WINDOWB_X_END;\ 492 473 type OTG_CRC0_WINDOWB_Y_START;\ 493 474 type OTG_CRC0_WINDOWB_Y_END;\ 475 + type OTG_CRC_WINDOW_DB_EN;\ 476 + type OTG_CRC1_WINDOWA_X_START;\ 477 + type OTG_CRC1_WINDOWA_X_END;\ 478 + type OTG_CRC1_WINDOWA_Y_START;\ 479 + type OTG_CRC1_WINDOWA_Y_END;\ 480 + type OTG_CRC1_WINDOWB_X_START;\ 481 + type OTG_CRC1_WINDOWB_X_END;\ 482 + type OTG_CRC1_WINDOWB_Y_START;\ 483 + type OTG_CRC1_WINDOWB_Y_END;\ 494 484 type GSL0_READY_SOURCE_SEL;\ 495 485 type GSL1_READY_SOURCE_SEL;\ 496 486 type GSL2_READY_SOURCE_SEL;\ ··· 552 524 553 525 #define TG_REG_FIELD_LIST_DCN3_2(type) \ 554 526 type OTG_H_TIMING_DIV_MODE_MANUAL; 527 + 555 528 556 529 struct dcn_optc_shift { 557 530 TG_REG_FIELD_LIST(uint8_t)
+2
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
··· 261 261 bool usb4_cm_version; 262 262 bool fw_in_system_memory; 263 263 bool dpia_hpd_int_enable_supported; 264 + bool disable_clock_gate; 265 + bool disallow_dispclk_dppclk_ds; 264 266 }; 265 267 266 268 /**
+1
drivers/gpu/drm/amd/display/include/dal_asic_id.h
··· 246 246 247 247 #define AMDGPU_FAMILY_GC_11_0_0 145 248 248 #define AMDGPU_FAMILY_GC_11_0_1 148 249 + #define AMDGPU_FAMILY_GC_11_5_0 150 249 250 #define GC_11_0_0_A0 0x1 250 251 #define GC_11_0_2_A0 0x10 251 252 #define GC_11_0_3_A0 0x20