drm/i915/hdmi: convert g4x_hdmi.[ch] to struct intel_display

+68 -71

drivers/gpu/drm/i915/display/g4x_hdmi.c

··· 27 27 static void intel_hdmi_prepare(struct intel_encoder *encoder, 28 28 const struct intel_crtc_state *crtc_state) 29 29 { 30 - struct drm_device *dev = encoder->base.dev; 31 - struct drm_i915_private *dev_priv = to_i915(dev); 30 + struct intel_display *display = to_intel_display(encoder); 31 + struct drm_i915_private *dev_priv = to_i915(display->drm); 32 32 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 33 33 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 34 34 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; ··· 54 54 55 55 if (HAS_PCH_CPT(dev_priv)) 56 56 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 57 - else if (IS_CHERRYVIEW(dev_priv)) 57 + else if (display->platform.cherryview) 58 58 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 59 59 else 60 60 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 61 61 62 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 63 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 62 + intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); 63 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 64 64 } 65 65 66 66 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, ··· 132 132 struct intel_crtc_state *crtc_state, 133 133 struct drm_connector_state *conn_state) 134 134 { 135 + struct intel_display *display = to_intel_display(encoder); 135 136 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 136 137 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 137 138 struct drm_i915_private *i915 = to_i915(encoder->base.dev); ··· 143 142 return -EINVAL; 144 143 } 145 144 146 - if (IS_G4X(i915)) 145 + if (display->platform.g4x) 147 146 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); 148 147 else 149 148 crtc_state->has_hdmi_sink = ··· 155 154 static void intel_hdmi_get_config(struct intel_encoder *encoder, 156 155 struct intel_crtc_state *pipe_config) 157 156 { 157 + struct intel_display *display = to_intel_display(encoder); 158 + struct drm_i915_private *dev_priv = to_i915(display->drm); 158 159 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 159 - struct drm_device *dev = encoder->base.dev; 160 - struct drm_i915_private *dev_priv = to_i915(dev); 161 160 u32 tmp, flags = 0; 162 161 int dotclock; 163 162 164 163 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 165 164 166 - tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 165 + tmp = intel_de_read(display, intel_hdmi->hdmi_reg); 167 166 168 167 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 169 168 flags |= DRM_MODE_FLAG_PHSYNC; ··· 223 222 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 224 223 const struct intel_crtc_state *pipe_config) 225 224 { 226 - struct drm_device *dev = encoder->base.dev; 227 - struct drm_i915_private *dev_priv = to_i915(dev); 225 + struct intel_display *display = to_intel_display(encoder); 228 226 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 229 227 u32 temp; 230 228 231 - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 229 + temp = intel_de_read(display, intel_hdmi->hdmi_reg); 232 230 233 231 temp |= SDVO_ENABLE; 234 232 235 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 236 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 233 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 234 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 237 235 } 238 236 239 237 static void g4x_hdmi_audio_enable(struct intel_encoder *encoder, 240 238 const struct intel_crtc_state *crtc_state, 241 239 const struct drm_connector_state *conn_state) 242 240 { 243 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 241 + struct intel_display *display = to_intel_display(encoder); 244 242 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 245 243 246 244 if (!crtc_state->has_audio) 247 245 return; 248 246 249 - drm_WARN_ON(&i915->drm, !crtc_state->has_hdmi_sink); 247 + drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink); 250 248 251 249 /* Enable audio presence detect */ 252 - intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); 250 + intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); 253 251 254 252 intel_audio_codec_enable(encoder, crtc_state, conn_state); 255 253 } ··· 257 257 const struct intel_crtc_state *old_crtc_state, 258 258 const struct drm_connector_state *old_conn_state) 259 259 { 260 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 260 + struct intel_display *display = to_intel_display(encoder); 261 261 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 262 262 263 263 if (!old_crtc_state->has_audio) ··· 266 266 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 267 267 268 268 /* Disable audio presence detect */ 269 - intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); 269 + intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); 270 270 } 271 271 272 272 static void g4x_enable_hdmi(struct intel_atomic_state *state, ··· 282 282 const struct intel_crtc_state *pipe_config, 283 283 const struct drm_connector_state *conn_state) 284 284 { 285 - struct drm_device *dev = encoder->base.dev; 286 - struct drm_i915_private *dev_priv = to_i915(dev); 285 + struct intel_display *display = to_intel_display(encoder); 287 286 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 288 287 u32 temp; 289 288 290 - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 289 + temp = intel_de_read(display, intel_hdmi->hdmi_reg); 291 290 292 291 temp |= SDVO_ENABLE; 293 292 ··· 294 295 * HW workaround, need to write this twice for issue 295 296 * that may result in first write getting masked. 296 297 */ 297 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 298 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 299 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 300 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 298 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 299 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 300 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 301 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 301 302 302 303 /* 303 304 * HW workaround, need to toggle enable bit off and on ··· 308 309 */ 309 310 if (pipe_config->pipe_bpp > 24 && 310 311 pipe_config->pixel_multiplier > 1) { 311 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 312 + intel_de_write(display, intel_hdmi->hdmi_reg, 312 313 temp & ~SDVO_ENABLE); 313 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 314 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 314 315 315 316 /* 316 317 * HW workaround, need to write this twice for issue 317 318 * that may result in first write getting masked. 318 319 */ 319 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 320 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 321 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 322 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 320 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 321 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 322 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 323 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 323 324 } 324 325 } 325 326 ··· 328 329 const struct intel_crtc_state *pipe_config, 329 330 const struct drm_connector_state *conn_state) 330 331 { 331 - struct drm_device *dev = encoder->base.dev; 332 - struct drm_i915_private *dev_priv = to_i915(dev); 332 + struct intel_display *display = to_intel_display(encoder); 333 333 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 334 334 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 335 335 enum pipe pipe = crtc->pipe; 336 336 u32 temp; 337 337 338 - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 338 + temp = intel_de_read(display, intel_hdmi->hdmi_reg); 339 339 340 340 temp |= SDVO_ENABLE; 341 341 ··· 349 351 */ 350 352 351 353 if (pipe_config->pipe_bpp > 24) { 352 - intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 354 + intel_de_rmw(display, TRANS_CHICKEN1(pipe), 353 355 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 354 356 355 357 temp &= ~SDVO_COLOR_FORMAT_MASK; 356 358 temp |= SDVO_COLOR_FORMAT_8bpc; 357 359 } 358 360 359 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 360 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 361 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 362 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 361 363 362 364 if (pipe_config->pipe_bpp > 24) { 363 365 temp &= ~SDVO_COLOR_FORMAT_MASK; 364 366 temp |= HDMI_COLOR_FORMAT_12bpc; 365 367 366 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 367 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 368 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 369 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 368 370 369 - intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 371 + intel_de_rmw(display, TRANS_CHICKEN1(pipe), 370 372 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 371 373 } 372 374 } ··· 384 386 const struct drm_connector_state *old_conn_state) 385 387 { 386 388 struct intel_display *display = to_intel_display(encoder); 387 - struct drm_device *dev = encoder->base.dev; 388 - struct drm_i915_private *dev_priv = to_i915(dev); 389 + struct drm_i915_private *dev_priv = to_i915(display->drm); 389 390 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 390 391 struct intel_digital_port *dig_port = 391 392 hdmi_to_dig_port(intel_hdmi); 392 393 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 393 394 u32 temp; 394 395 395 - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 396 + temp = intel_de_read(display, intel_hdmi->hdmi_reg); 396 397 397 398 temp &= ~SDVO_ENABLE; 398 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 399 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 399 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 400 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 400 401 401 402 /* 402 403 * HW workaround for IBX, we need to move the port ··· 416 419 * HW workaround, need to write this twice for issue 417 420 * that may result in first write getting masked. 418 421 */ 419 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 420 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 421 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 422 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 422 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 423 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 424 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 425 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 423 426 424 427 temp &= ~SDVO_ENABLE; 425 - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 426 - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 428 + intel_de_write(display, intel_hdmi->hdmi_reg, temp); 429 + intel_de_posting_read(display, intel_hdmi->hdmi_reg); 427 430 428 431 intel_wait_for_vblank_if_active(display, PIPE_A); 429 432 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); ··· 541 544 const struct intel_crtc_state *old_crtc_state, 542 545 const struct drm_connector_state *old_conn_state) 543 546 { 544 - struct drm_device *dev = encoder->base.dev; 545 - struct drm_i915_private *dev_priv = to_i915(dev); 547 + struct intel_display *display = to_intel_display(encoder); 548 + struct drm_i915_private *dev_priv = to_i915(display->drm); 546 549 547 550 vlv_dpio_get(dev_priv); 548 551 ··· 611 614 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 612 615 struct drm_atomic_state *state) 613 616 { 614 - struct drm_i915_private *i915 = to_i915(state->dev); 617 + struct intel_display *display = to_intel_display(connector->dev); 615 618 struct drm_connector_list_iter conn_iter; 616 619 struct drm_connector *conn; 617 620 int ret; ··· 620 623 if (ret) 621 624 return ret; 622 625 623 - if (!IS_G4X(i915)) 626 + if (!display->platform.g4x) 624 627 return 0; 625 628 626 629 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) ··· 634 637 * 635 638 * See also g4x_compute_has_hdmi_sink(). 636 639 */ 637 - drm_connector_list_iter_begin(&i915->drm, &conn_iter); 640 + drm_connector_list_iter_begin(display->drm, &conn_iter); 638 641 drm_for_each_connector_iter(conn, &conn_iter) { 639 642 struct drm_connector_state *conn_state; 640 643 struct drm_crtc_state *crtc_state; ··· 643 646 if (!connector_is_hdmi(conn)) 644 647 continue; 645 648 646 - drm_dbg_kms(&i915->drm, "Adding [CONNECTOR:%d:%s]\n", 649 + drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n", 647 650 conn->base.id, conn->name); 648 651 649 652 conn_state = drm_atomic_get_connector_state(state, conn); ··· 668 671 return ret; 669 672 } 670 673 671 - static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 674 + static bool is_hdmi_port_valid(struct intel_display *display, enum port port) 672 675 { 673 - if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) 676 + if (display->platform.g4x || display->platform.valleyview) 674 677 return port == PORT_B || port == PORT_C; 675 678 else 676 679 return port == PORT_B || port == PORT_C || port == PORT_D; 677 680 } 678 681 679 - static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 682 + static bool assert_hdmi_port_valid(struct intel_display *display, enum port port) 680 683 { 681 - return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port), 684 + return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port), 682 685 "Platform does not support HDMI %c\n", port_name(port)); 683 686 } 684 687 685 - bool g4x_hdmi_init(struct drm_i915_private *dev_priv, 688 + bool g4x_hdmi_init(struct intel_display *display, 686 689 i915_reg_t hdmi_reg, enum port port) 687 690 { 688 - struct intel_display *display = &dev_priv->display; 691 + struct drm_i915_private *dev_priv = to_i915(display->drm); 689 692 const struct intel_bios_encoder_data *devdata; 690 693 struct intel_digital_port *dig_port; 691 694 struct intel_encoder *intel_encoder; ··· 694 697 if (!assert_port_valid(dev_priv, port)) 695 698 return false; 696 699 697 - if (!assert_hdmi_port_valid(dev_priv, port)) 700 + if (!assert_hdmi_port_valid(display, port)) 698 701 return false; 699 702 700 703 devdata = intel_bios_encoder_data_lookup(display, port); 701 704 702 705 /* FIXME bail? */ 703 706 if (!devdata) 704 - drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n", 707 + drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n", 705 708 port_name(port)); 706 709 707 710 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); ··· 720 723 721 724 mutex_init(&dig_port->hdcp_mutex); 722 725 723 - if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 726 + if (drm_encoder_init(display->drm, &intel_encoder->base, 724 727 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 725 728 "HDMI %c", port_name(port))) 726 729 goto err_encoder_init; ··· 735 738 } 736 739 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 737 740 intel_encoder->get_config = intel_hdmi_get_config; 738 - if (IS_CHERRYVIEW(dev_priv)) { 741 + if (display->platform.cherryview) { 739 742 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 740 743 intel_encoder->pre_enable = chv_hdmi_pre_enable; 741 744 intel_encoder->enable = vlv_enable_hdmi; 742 745 intel_encoder->post_disable = chv_hdmi_post_disable; 743 746 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 744 - } else if (IS_VALLEYVIEW(dev_priv)) { 747 + } else if (display->platform.valleyview) { 745 748 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 746 749 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 747 750 intel_encoder->enable = vlv_enable_hdmi; ··· 762 765 intel_encoder->type = INTEL_OUTPUT_HDMI; 763 766 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 764 767 intel_encoder->port = port; 765 - if (IS_CHERRYVIEW(dev_priv)) { 768 + if (display->platform.cherryview) { 766 769 if (port == PORT_D) 767 770 intel_encoder->pipe_mask = BIT(PIPE_C); 768 771 else ··· 777 780 * to work on real hardware. And since g4x can send infoframes to 778 781 * only one port anyway, nothing is lost by allowing it. 779 782 */ 780 - if (IS_G4X(dev_priv)) 783 + if (display->platform.g4x) 781 784 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 782 785 783 786 dig_port->hdmi.hdmi_reg = hdmi_reg;

+3 -3

drivers/gpu/drm/i915/display/g4x_hdmi.h

··· 13 13 enum port; 14 14 struct drm_atomic_state; 15 15 struct drm_connector; 16 - struct drm_i915_private; 16 + struct intel_display; 17 17 18 18 #ifdef I915 19 - bool g4x_hdmi_init(struct drm_i915_private *dev_priv, 19 + bool g4x_hdmi_init(struct intel_display *display, 20 20 i915_reg_t hdmi_reg, enum port port); 21 21 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 22 22 struct drm_atomic_state *state); 23 23 #else 24 - static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv, 24 + static inline bool g4x_hdmi_init(struct intel_display *display, 25 25 i915_reg_t hdmi_reg, int port) 26 26 { 27 27 return false;

+8 -8

drivers/gpu/drm/i915/display/intel_display.c

··· 8234 8234 /* PCH SDVOB multiplex with HDMIB */ 8235 8235 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); 8236 8236 if (!found) 8237 - g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); 8237 + g4x_hdmi_init(display, PCH_HDMIB, PORT_B); 8238 8238 if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) 8239 8239 g4x_dp_init(display, PCH_DP_B, PORT_B); 8240 8240 } 8241 8241 8242 8242 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) 8243 - g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); 8243 + g4x_hdmi_init(display, PCH_HDMIC, PORT_C); 8244 8244 8245 8245 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) 8246 - g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); 8246 + g4x_hdmi_init(display, PCH_HDMID, PORT_D); 8247 8247 8248 8248 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) 8249 8249 g4x_dp_init(display, PCH_DP_C, PORT_C); ··· 8276 8276 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) 8277 8277 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); 8278 8278 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 8279 - g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); 8279 + g4x_hdmi_init(display, VLV_HDMIB, PORT_B); 8280 8280 8281 8281 has_edp = intel_dp_is_port_edp(display, PORT_C); 8282 8282 has_port = intel_bios_is_port_present(display, PORT_C); 8283 8283 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) 8284 8284 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); 8285 8285 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 8286 - g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); 8286 + g4x_hdmi_init(display, VLV_HDMIC, PORT_C); 8287 8287 8288 8288 if (IS_CHERRYVIEW(dev_priv)) { 8289 8289 /* ··· 8294 8294 if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) 8295 8295 g4x_dp_init(display, CHV_DP_D, PORT_D); 8296 8296 if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) 8297 - g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); 8297 + g4x_hdmi_init(display, CHV_HDMID, PORT_D); 8298 8298 } 8299 8299 8300 8300 vlv_dsi_init(dev_priv); ··· 8315 8315 if (!found && IS_G4X(dev_priv)) { 8316 8316 drm_dbg_kms(&dev_priv->drm, 8317 8317 "probing HDMI on SDVOB\n"); 8318 - g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); 8318 + g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); 8319 8319 } 8320 8320 8321 8321 if (!found && IS_G4X(dev_priv)) ··· 8334 8334 if (IS_G4X(dev_priv)) { 8335 8335 drm_dbg_kms(&dev_priv->drm, 8336 8336 "probing HDMI on SDVOC\n"); 8337 - g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); 8337 + g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); 8338 8338 } 8339 8339 if (IS_G4X(dev_priv)) 8340 8340 g4x_dp_init(display, DP_C, PORT_C);