tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees
Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
authored by
Alexander Stein
and committed by
Shawn Guo
a333f3e4
7b8861d8
+135
+1
arch/arm/boot/dts/Makefile
+1
arch/arm/boot/dts/Makefile
+15
arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
+15
arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2
+
/*
3
+
* Copyright 2018-2022 TQ Systems GmbH
4
+
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
5
+
*/
6
+
7
+
/dts-v1/;
8
+
9
+
#include "imx6ul-tqma6ul2l.dtsi"
10
+
#include "mba6ulx.dtsi"
11
+
12
+
/ {
13
+
model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board";
14
+
compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
15
+
};
+71
arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
+71
arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2
+
/*
3
+
* Copyright 2018-2022 TQ-Systems GmbH
4
+
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
5
+
*/
6
+
7
+
#include "imx6ul.dtsi"
8
+
#include "imx6ul-tqma6ul-common.dtsi"
9
+
#include "imx6ul-tqma6ulxl-common.dtsi"
10
+
11
+
/ {
12
+
model = "TQ-Systems TQMa6UL2L SoM";
13
+
compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
14
+
};
15
+
16
+
&usdhc2 {
17
+
fsl,tuning-step= <6>;
18
+
};
19
+
20
+
&iomuxc {
21
+
pinctrl_usdhc2: usdhc2grp {
22
+
fsl,pins = <
23
+
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051
24
+
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051
25
+
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051
26
+
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051
27
+
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051
28
+
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051
29
+
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051
30
+
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051
31
+
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051
32
+
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051
33
+
/* rst */
34
+
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
35
+
>;
36
+
};
37
+
38
+
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
39
+
fsl,pins = <
40
+
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1
41
+
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
42
+
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
43
+
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
44
+
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
45
+
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
46
+
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
47
+
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
48
+
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
49
+
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
50
+
/* rst */
51
+
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
52
+
>;
53
+
};
54
+
55
+
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
56
+
fsl,pins = <
57
+
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9
58
+
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1
59
+
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1
60
+
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1
61
+
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1
62
+
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1
63
+
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1
64
+
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1
65
+
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1
66
+
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1
67
+
/* rst */
68
+
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051
69
+
>;
70
+
};
71
+
};
+48
arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
+48
arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2
+
/*
3
+
* Copyright 2018-2022 TQ-Systems GmbH
4
+
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
5
+
*/
6
+
7
+
/*
8
+
* Common for
9
+
* - TQMa6ULxL
10
+
* - TQMa6ULLxL
11
+
*/
12
+
13
+
/ {
14
+
reg_vin: reg-vin {
15
+
compatible = "regulator-fixed";
16
+
regulator-name = "VIN";
17
+
regulator-min-microvolt = <3300000>;
18
+
regulator-max-microvolt = <3300000>;
19
+
regulator-always-on;
20
+
};
21
+
};
22
+
23
+
&m24c64_50 {
24
+
vcc-supply = <®_vin>;
25
+
};
26
+
27
+
&m24c02_52 {
28
+
vcc-supply = <®_vin>;
29
+
};
30
+
31
+
/* eMMC */
32
+
&usdhc2 {
33
+
vmmc-supply = <®_vin>;
34
+
vqmmc-supply = <®_vldo4>;
35
+
};
36
+
37
+
&iomuxc {
38
+
pinctrl_qspi: qspigrp {
39
+
fsl,pins = <
40
+
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9
41
+
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9
42
+
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9
43
+
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9
44
+
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9
45
+
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
46
+
>;
47
+
};
48
+
};