Staging: bcm: DDRInit: fix up some bracing issues.

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

I fixed some brace coding style issues.

Signed-off-by: Gary Alan Rookard <garyrookard@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Gary Rookard and committed by

Greg Kroah-Hartman 12 years ago a320dd83 d3055585

+30 -77

1 changed file

expand all

drivers

staging

bcm

DDRInit.c

+30 -77

drivers/staging/bcm/DDRInit.c

··· 780 780 UINT uiClockSetting = 0; 781 781 int retval = STATUS_SUCCESS; 782 782 783 - switch (Adapter->chip_id) 784 - { 783 + switch (Adapter->chip_id) { 785 784 case 0xbece3200: 786 - switch (Adapter->DDRSetting) 787 - { 785 + switch (Adapter->DDRSetting) { 788 786 case DDR_80_MHZ: 789 787 psDDRSetting = asT3LP_DDRSetting80MHz; 790 788 RegCount = (sizeof(asT3LP_DDRSetting80MHz)/ ··· 798 800 RegCount = (sizeof(asT3LP_DDRSetting133MHz)/ 799 801 sizeof(struct bcm_ddr_setting)); 800 802 if (Adapter->bMipsConfig == MIPS_200_MHZ) 801 - { 802 803 uiClockSetting = 0x03F13652; 803 - } 804 804 else 805 - { 806 805 uiClockSetting = 0x03F1365B; 807 - } 808 806 break; 809 807 default: 810 808 return -EINVAL; 811 - } 809 + } 812 810 813 811 break; 814 812 case T3LPB: ··· 817 823 */ 818 824 if ((Adapter->chip_id != BCS220_2) && 819 825 (Adapter->chip_id != BCS220_2BC) && 820 - (Adapter->chip_id != BCS220_3)) 821 - { 826 + (Adapter->chip_id != BCS220_3)) { 822 827 retval = rdmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue)); 823 828 if (retval < 0) { 824 829 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__); 825 830 return retval; 826 - } 831 + } 827 832 uiResetValue |= 0x44; 828 833 retval = wrmalt(Adapter,(UINT)0x0f000830, &uiResetValue, sizeof(uiResetValue)); 829 834 if (retval < 0) { 830 835 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__); 831 836 return retval; 832 - } 833 837 } 834 - switch (Adapter->DDRSetting) 835 - { 838 + } 839 + switch (Adapter->DDRSetting) { 836 840 837 841 838 842 ··· 850 858 sizeof(struct bcm_ddr_setting)); 851 859 852 860 if (Adapter->bMipsConfig == MIPS_200_MHZ) 853 - { 854 861 uiClockSetting = 0x03F13652; 855 - } 856 862 else 857 - { 858 863 uiClockSetting = 0x03F1365B; 859 - } 860 864 break; 861 865 862 866 case DDR_160_MHZ: ··· 860 872 RegCount = sizeof(asT3LPB_DDRSetting160MHz)/sizeof(struct bcm_ddr_setting); 861 873 862 874 if (Adapter->bMipsConfig == MIPS_200_MHZ) 863 - { 864 875 uiClockSetting = 0x03F137D2; 865 - } 866 876 else 867 - { 868 877 uiClockSetting = 0x03F137DB; 869 - } 870 - } 878 + } 871 879 break; 872 880 873 881 case 0xbece0110: ··· 872 888 case 0xbece0130: 873 889 case 0xbece0300: 874 890 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "DDR Setting: %x\n", Adapter->DDRSetting); 875 - switch (Adapter->DDRSetting) 876 - { 891 + switch (Adapter->DDRSetting) { 877 892 case DDR_80_MHZ: 878 893 psDDRSetting = asT3_DDRSetting80MHz; 879 894 RegCount = (sizeof(asT3_DDRSetting80MHz)/ ··· 893 910 } 894 911 case 0xbece0310: 895 912 { 896 - switch (Adapter->DDRSetting) 897 - { 913 + switch (Adapter->DDRSetting) { 898 914 case DDR_80_MHZ: 899 915 psDDRSetting = asT3B_DDRSetting80MHz; 900 916 RegCount = (sizeof(asT3B_DDRSetting80MHz)/ ··· 906 924 break; 907 925 case DDR_133_MHZ: 908 926 909 - if (Adapter->bDPLLConfig == PLL_266_MHZ) /* 266Mhz PLL selected. */ 910 - { 927 + if (Adapter->bDPLLConfig == PLL_266_MHZ) { /* 266Mhz PLL selected. */ 911 928 memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ, 912 929 sizeof(asDPLL_266MHZ)); 913 930 psDDRSetting = asT3B_DDRSetting133MHz; 914 931 RegCount = (sizeof(asT3B_DDRSetting133MHz)/ 915 932 sizeof(struct bcm_ddr_setting)); 916 - } 917 - else 918 - { 933 + } else { 919 934 psDDRSetting = asT3B_DDRSetting133MHz; 920 935 RegCount = (sizeof(asT3B_DDRSetting133MHz)/ 921 936 sizeof(struct bcm_ddr_setting)); 922 937 if (Adapter->bMipsConfig == MIPS_200_MHZ) 923 - { 924 938 uiClockSetting = 0x07F13652; 925 - } 926 939 else 927 - { 928 940 uiClockSetting = 0x07F1365B; 929 - } 930 - } 941 + } 931 942 break; 932 943 default: 933 944 return -EINVAL; ··· 934 959 935 960 value = 0; 936 961 BCM_DEBUG_PRINT(Adapter,DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL, "Register Count is =%lu\n", RegCount); 937 - while (RegCount && !retval) 938 - { 962 + while (RegCount && !retval) { 939 963 if (uiClockSetting && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG) 940 - { 941 964 value = uiClockSetting; 942 - } 943 965 else 944 - { 945 966 value = psDDRSetting->ulRegValue; 946 - } 947 967 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, &value, sizeof(value)); 948 968 if (STATUS_SUCCESS != retval) { 949 969 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__); ··· 949 979 psDDRSetting++; 950 980 } 951 981 952 - if (Adapter->chip_id >= 0xbece3300) 953 - { 982 + if (Adapter->chip_id >= 0xbece3300) { 954 983 955 984 mdelay(3); 956 985 if ((Adapter->chip_id != BCS220_2) && 957 986 (Adapter->chip_id != BCS220_2BC) && 958 - (Adapter->chip_id != BCS220_3)) 959 - { 987 + (Adapter->chip_id != BCS220_3)) { 960 988 /* drive MDDR to half in case of UMA-B: */ 961 989 uiResetValue = 0x01010001; 962 990 retval = wrmalt(Adapter, (UINT)0x0F007018, &uiResetValue, sizeof(uiResetValue)); ··· 989 1021 * and since we dont have internal PMU lets do it under UMA-B chip id. 990 1022 * we will change this when we will have internal PMU. 991 1023 */ 992 - if (Adapter->PmuMode == HYBRID_MODE_7C) 993 - { 1024 + if (Adapter->PmuMode == HYBRID_MODE_7C) { 994 1025 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue)); 995 1026 if (retval < 0) { 996 1027 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__); ··· 1022 1055 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL, "%s:%d RDM failed\n", __func__, __LINE__); 1023 1056 return retval; 1024 1057 } 1025 - } 1026 - else if (Adapter->PmuMode == HYBRID_MODE_6) 1027 - { 1058 + } else if (Adapter->PmuMode == HYBRID_MODE_6) { 1028 1059 1029 1060 retval = rdmalt(Adapter,(UINT)0x0f000c00, &uiResetValue, sizeof(uiResetValue)); 1030 1061 if (retval < 0) { ··· 1072 1107 int retval = STATUS_SUCCESS; 1073 1108 bool bOverrideSelfRefresh = false; 1074 1109 1075 - switch (Adapter->chip_id) 1076 - { 1110 + switch (Adapter->chip_id) { 1077 1111 case 0xbece3200: 1078 - switch (Adapter->DDRSetting) 1079 - { 1112 + switch (Adapter->DDRSetting) { 1080 1113 case DDR_80_MHZ: 1081 1114 psDDRSetting = asT3LP_DDRSetting80MHz; 1082 1115 RegCount = ARRAY_SIZE(asT3LP_DDRSetting80MHz); ··· 1104 1141 case BCS220_2BC: 1105 1142 case BCS250_BC: 1106 1143 case BCS220_3: 1107 - switch (Adapter->DDRSetting) 1108 - { 1144 + switch (Adapter->DDRSetting) { 1109 1145 case DDR_80_MHZ: 1110 1146 psDDRSetting = asT3LPB_DDRSetting80MHz; 1111 1147 RegCount = ARRAY_SIZE(asT3LPB_DDRSetting80MHz); ··· 1138 1176 } 1139 1177 break; 1140 1178 case 0xbece0300: 1141 - switch (Adapter->DDRSetting) 1142 - { 1179 + switch (Adapter->DDRSetting) { 1143 1180 case DDR_80_MHZ: 1144 1181 psDDRSetting = asT3_DDRSetting80MHz; 1145 1182 RegCount = ARRAY_SIZE(asT3_DDRSetting80MHz); ··· 1163 1202 break; 1164 1203 case 0xbece0310: 1165 1204 { 1166 - switch (Adapter->DDRSetting) 1167 - { 1205 + switch (Adapter->DDRSetting) { 1168 1206 case DDR_80_MHZ: 1169 1207 psDDRSetting = asT3B_DDRSetting80MHz; 1170 1208 RegCount = ARRAY_SIZE(asT3B_DDRSetting80MHz); ··· 1183 1223 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ; 1184 1224 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ; 1185 1225 break; 1186 - } 1226 + } 1187 1227 break; 1188 1228 } 1189 1229 default: ··· 1192 1232 /* total number of Register that has to be dumped */ 1193 1233 value = RegCount; 1194 1234 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value)); 1195 - if (retval) 1196 - { 1235 + if (retval) { 1197 1236 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__); 1198 1237 1199 1238 return retval; ··· 1201 1242 /* signature */ 1202 1243 value = (0x1d1e0dd0); 1203 1244 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value)); 1204 - if (retval) 1205 - { 1245 + if (retval) { 1206 1246 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__); 1207 1247 return retval; 1208 1248 } ··· 1209 1251 ul_ddr_setting_load_addr += sizeof(ULONG); 1210 1252 RegCount *= (sizeof(struct bcm_ddr_setting)/sizeof(ULONG)); 1211 1253 1212 - while (RegCount && !retval) 1213 - { 1254 + while (RegCount && !retval) { 1214 1255 value = psDDRSetting->ulRegAddress; 1215 1256 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value, sizeof(value)); 1216 1257 ul_ddr_setting_load_addr += sizeof(ULONG); 1217 - if (!retval) 1218 - { 1219 - if (bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018)) 1220 - { 1258 + if (!retval) { 1259 + if (bOverrideSelfRefresh && (psDDRSetting->ulRegAddress == 0x0F007018)) { 1221 1260 value = (psDDRSetting->ulRegValue |(1<<8)); 1222 1261 if (STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr, 1223 1262 &value, sizeof(value))) { 1224 1263 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0, "%s:%d\n", __func__, __LINE__); 1225 1264 break; 1226 - } 1227 1265 } 1228 - else 1229 - { 1266 + } else { 1230 1267 value = psDDRSetting->ulRegValue; 1231 1268 1232 1269 if (STATUS_SUCCESS != wrmalt(Adapter, ul_ddr_setting_load_addr ,