Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/pm: support return vpe clock table

pm supports return vpe clock table and soc clock table

Signed-off-by: Peyton Lee <peytolee@amd.com>
Reviewed-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Peyton Lee and committed by
Alex Deucher
a2f2f43f 94aeb411

+33
+2
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
··· 247 247 #define PP_SMU_NUM_MEMCLK_DPM_LEVELS 4 248 248 #define PP_SMU_NUM_DCLK_DPM_LEVELS 8 249 249 #define PP_SMU_NUM_VCLK_DPM_LEVELS 8 250 + #define PP_SMU_NUM_VPECLK_DPM_LEVELS 8 250 251 251 252 struct dpm_clock { 252 253 uint32_t Freq; // In MHz ··· 263 262 struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS]; 264 263 struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS]; 265 264 struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS]; 265 + struct dpm_clock VPEClocks[PP_SMU_NUM_VPECLK_DPM_LEVELS]; 266 266 }; 267 267 268 268
+10
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
··· 616 616 enable ? "enable" : "disable", ret); 617 617 } 618 618 619 + void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) 620 + { 621 + int ret = 0; 622 + 623 + ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable); 624 + if (ret) 625 + DRM_ERROR("Dpm %s vpe failed, ret = %d.\n", 626 + enable ? "enable" : "disable", ret); 627 + } 628 + 619 629 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) 620 630 { 621 631 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+1
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
··· 445 445 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); 446 446 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); 447 447 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); 448 + void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable); 448 449 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); 449 450 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); 450 451 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
+20
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
··· 1085 1085 0, NULL); 1086 1086 } 1087 1087 1088 + static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) 1089 + { 1090 + DpmClocks_t *clk_table = smu->smu_table.clocks_table; 1091 + uint8_t idx; 1092 + 1093 + /* Only the Clock information of SOC and VPE is copied to provide VPE DPM settings for use. */ 1094 + for (idx = 0; idx < NUM_SOCCLK_DPM_LEVELS; idx++) { 1095 + clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClocks[idx]:0; 1096 + clock_table->SocClocks[idx].Vol = 0; 1097 + } 1098 + 1099 + for (idx = 0; idx < NUM_VPE_DPM_LEVELS; idx++) { 1100 + clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[idx]:0; 1101 + clock_table->VPEClocks[idx].Vol = 0; 1102 + } 1103 + 1104 + return 0; 1105 + } 1106 + 1088 1107 static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { 1089 1108 .check_fw_status = smu_v14_0_check_fw_status, 1090 1109 .check_fw_version = smu_v14_0_check_fw_version, ··· 1134 1115 .set_gfx_power_up_by_imu = smu_v14_0_set_gfx_power_up_by_imu, 1135 1116 .dpm_set_vpe_enable = smu_v14_0_0_set_vpe_enable, 1136 1117 .dpm_set_umsch_mm_enable = smu_v14_0_0_set_umsch_mm_enable, 1118 + .get_dpm_clock_table = smu_14_0_0_get_dpm_table, 1137 1119 }; 1138 1120 1139 1121 static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)