tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/exynos: mixer: set window priority based on zpos

'zpos' plane property is configurable, so adjust hardware layers
priority based on the zpos value. 'zpos' value shifted by one can be
used directly as hw priority value and stored to the registers, because
mixer accepts priority values from 1 to 15 (0 means that layer is
disabled).

This patch also changes the default layer priority to match already
exposed initial zpos values. The initial configuration is now:
[top] video > gfx layer1 > gfx layer0 [bottom].

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

authored by

Marek Szyprowski and committed by
Inki Dae a2cb911e 0ea72405

+24 -18
+21 -18
drivers/gpu/drm/exynos/exynos_mixer.c
··· 117 117 .type = DRM_PLANE_TYPE_PRIMARY, 118 118 .pixel_formats = mixer_formats, 119 119 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 120 - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, 120 + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | 121 + EXYNOS_DRM_PLANE_CAP_ZPOS, 121 122 }, { 122 123 .zpos = 1, 123 124 .type = DRM_PLANE_TYPE_CURSOR, 124 125 .pixel_formats = mixer_formats, 125 126 .num_pixel_formats = ARRAY_SIZE(mixer_formats), 126 - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, 127 + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | 128 + EXYNOS_DRM_PLANE_CAP_ZPOS, 127 129 }, { 128 130 .zpos = 2, 129 131 .type = DRM_PLANE_TYPE_OVERLAY, 130 132 .pixel_formats = vp_formats, 131 133 .num_pixel_formats = ARRAY_SIZE(vp_formats), 132 - .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE, 134 + .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | 135 + EXYNOS_DRM_PLANE_CAP_ZPOS, 133 136 }, 134 137 }; 135 138 ··· 375 372 } 376 373 377 374 static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, 378 - bool enable) 375 + unsigned int priority, bool enable) 379 376 { 380 377 struct mixer_resources *res = &ctx->mixer_res; 381 378 u32 val = enable ? ~0 : 0; ··· 383 380 switch (win) { 384 381 case 0: 385 382 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); 383 + mixer_reg_writemask(res, MXR_LAYER_CFG, 384 + MXR_LAYER_CFG_GRP0_VAL(priority), 385 + MXR_LAYER_CFG_GRP0_MASK); 386 386 break; 387 387 case 1: 388 388 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); 389 + mixer_reg_writemask(res, MXR_LAYER_CFG, 390 + MXR_LAYER_CFG_GRP1_VAL(priority), 391 + MXR_LAYER_CFG_GRP1_MASK); 389 392 break; 390 393 case 2: 391 394 if (ctx->vp_enabled) { 392 395 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); 393 396 mixer_reg_writemask(res, MXR_CFG, val, 394 397 MXR_CFG_VP_ENABLE); 398 + mixer_reg_writemask(res, MXR_LAYER_CFG, 399 + MXR_LAYER_CFG_VP_VAL(priority), 400 + MXR_LAYER_CFG_VP_MASK); 395 401 396 402 /* control blending of graphic layer 0 */ 397 403 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val, ··· 523 511 524 512 mixer_cfg_scan(ctx, mode->vdisplay); 525 513 mixer_cfg_rgb_fmt(ctx, mode->vdisplay); 526 - mixer_cfg_layer(ctx, plane->index, true); 514 + mixer_cfg_layer(ctx, plane->index, state->zpos + 1, true); 527 515 mixer_run(ctx); 528 516 529 517 mixer_vsync_set_update(ctx, true); ··· 638 626 639 627 mixer_cfg_scan(ctx, mode->vdisplay); 640 628 mixer_cfg_rgb_fmt(ctx, mode->vdisplay); 641 - mixer_cfg_layer(ctx, win, true); 629 + mixer_cfg_layer(ctx, win, state->zpos + 1, true); 642 630 643 631 /* layer update mandatory for mixer 16.0.33.0 */ 644 632 if (ctx->mxr_ver == MXR_VER_16_0_33_0 || ··· 686 674 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, 687 675 MXR_STATUS_BURST_MASK); 688 676 689 - /* setting default layer priority: layer1 > layer0 > video 690 - * because typical usage scenario would be 691 - * layer1 - OSD 692 - * layer0 - framebuffer 693 - * video - video overlay 694 - */ 695 - val = MXR_LAYER_CFG_GRP1_VAL(3); 696 - val |= MXR_LAYER_CFG_GRP0_VAL(2); 697 - if (ctx->vp_enabled) 698 - val |= MXR_LAYER_CFG_VP_VAL(1); 699 - mixer_reg_write(res, MXR_LAYER_CFG, val); 677 + /* reset default layer priority */ 678 + mixer_reg_write(res, MXR_LAYER_CFG, 0); 700 679 701 680 /* setting background color */ 702 681 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080); ··· 985 982 spin_lock_irqsave(&res->reg_slock, flags); 986 983 mixer_vsync_set_update(mixer_ctx, false); 987 984 988 - mixer_cfg_layer(mixer_ctx, plane->index, false); 985 + mixer_cfg_layer(mixer_ctx, plane->index, 0, false); 989 986 990 987 mixer_vsync_set_update(mixer_ctx, true); 991 988 spin_unlock_irqrestore(&res->reg_slock, flags);
+3
drivers/gpu/drm/exynos/regs-mixer.h
··· 145 145 146 146 /* bit for MXR_LAYER_CFG */ 147 147 #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) 148 + #define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0) 148 149 #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) 150 + #define MXR_LAYER_CFG_GRP0_MASK MXR_LAYER_CFG_GRP0_VAL(~0) 149 151 #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) 152 + #define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0) 150 153 151 154 #endif /* SAMSUNG_REGS_MIXER_H */ 152 155