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tools/memory-model: glossary.txt: Fix indents

There are a couple of inconsistent indents around code/literal blocks.
Adjust them to make this file easier to parse.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
Signed-off-by: Paul E. McKenney <paulmck@kernel.org>

authored by

Akira Yokosawa and committed by
Paul E. McKenney
a2bfbf84 fa9e35a0

+16 -16
+16 -16
tools/memory-model/Documentation/glossary.txt
··· 15 15 3 do_something(p->a); 16 16 4 rcu_read_unlock(); 17 17 18 - In this case, because the address of "p->a" on line 3 is computed 19 - from the value returned by the rcu_dereference() on line 2, the 20 - address dependency extends from that rcu_dereference() to that 21 - "p->a". In rare cases, optimizing compilers can destroy address 22 - dependencies. Please see Documentation/RCU/rcu_dereference.rst 23 - for more information. 18 + In this case, because the address of "p->a" on line 3 is computed 19 + from the value returned by the rcu_dereference() on line 2, the 20 + address dependency extends from that rcu_dereference() to that 21 + "p->a". In rare cases, optimizing compilers can destroy address 22 + dependencies. Please see Documentation/RCU/rcu_dereference.rst 23 + for more information. 24 24 25 - See also "Control Dependency" and "Data Dependency". 25 + See also "Control Dependency" and "Data Dependency". 26 26 27 27 Acquire: With respect to a lock, acquiring that lock, for example, 28 28 using spin_lock(). With respect to a non-lock shared variable, ··· 59 59 1 if (READ_ONCE(x)) 60 60 2 WRITE_ONCE(y, 1); 61 61 62 - Here, the control dependency extends from the READ_ONCE() on 63 - line 1 to the WRITE_ONCE() on line 2. Control dependencies are 64 - fragile, and can be easily destroyed by optimizing compilers. 65 - Please see control-dependencies.txt for more information. 62 + Here, the control dependency extends from the READ_ONCE() on 63 + line 1 to the WRITE_ONCE() on line 2. Control dependencies are 64 + fragile, and can be easily destroyed by optimizing compilers. 65 + Please see control-dependencies.txt for more information. 66 66 67 - See also "Address Dependency" and "Data Dependency". 67 + See also "Address Dependency" and "Data Dependency". 68 68 69 69 Cycle: Memory-barrier pairing is restricted to a pair of CPUs, as the 70 70 name suggests. And in a great many cases, a pair of CPUs is all ··· 72 72 extended to additional CPUs, and the result is called a "cycle". 73 73 In a cycle, each CPU's ordering interacts with that of the next: 74 74 75 - CPU 0 CPU 1 CPU 2 76 - WRITE_ONCE(x, 1); WRITE_ONCE(y, 1); WRITE_ONCE(z, 1); 77 - smp_mb(); smp_mb(); smp_mb(); 78 - r0 = READ_ONCE(y); r1 = READ_ONCE(z); r2 = READ_ONCE(x); 75 + CPU 0 CPU 1 CPU 2 76 + WRITE_ONCE(x, 1); WRITE_ONCE(y, 1); WRITE_ONCE(z, 1); 77 + smp_mb(); smp_mb(); smp_mb(); 78 + r0 = READ_ONCE(y); r1 = READ_ONCE(z); r2 = READ_ONCE(x); 79 79 80 80 CPU 0's smp_mb() interacts with that of CPU 1, which interacts 81 81 with that of CPU 2, which in turn interacts with that of CPU 0