tjh.dev / kernel
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MIPS: Move r4k FP code from r4k_switch.S to r4k_fpu.S

Move _save_fp(), _restore_fp(), _save_msa(), _restore_msa(),
_init_msa_upper() & _init_fpu() out of r4k_switch.S & into r4k_fpu.S.
This allows us to clean up the way in which Octeon includes the default
r4k implementations of these FP functions despite replacing resume(),
and makes CONFIG_R4K_FPU more straightforwardly represent all
configurations that have an R4K-style FPU, including Octeon.

Besides cleaning up this will be useful for later patches which disable
FP support.

[ralf@linux-mips.org: Fixed build issues reported by Arnd Bergmann
<arnd@arndb.de>]

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16237/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Paul Burton and committed by
Ralf Baechle a2aea699 3b2db173

+212 -213
+1 -1
arch/mips/Kconfig
··· 2241 2241 2242 2242 config CPU_R4K_FPU 2243 2243 bool 2244 - default y if !(CPU_R3000 || CPU_TX39XX || CPU_CAVIUM_OCTEON) 2244 + default y if !(CPU_R3000 || CPU_TX39XX) 2245 2245 2246 2246 config CPU_R4K_CACHE_TLB 2247 2247 bool
+9 -4
arch/mips/kernel/Makefile
··· 35 35 obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o 36 36 obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o 37 37 38 - obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o 39 - obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 40 - obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 41 - obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o 38 + sw-y := r4k_switch.o 39 + sw-$(CONFIG_CPU_R3000) := r2300_switch.o 40 + sw-$(CONFIG_CPU_TX39XX) := r2300_switch.o 41 + sw-$(CONFIG_CPU_CAVIUM_OCTEON) := octeon_switch.o 42 + obj-y += $(sw-y) 43 + 44 + obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o 45 + obj-$(CONFIG_CPU_R3000) += r2300_fpu.o 46 + obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o 42 47 43 48 obj-$(CONFIG_SMP) += smp.o 44 49 obj-$(CONFIG_SMP_UP) += smp-up.o
+6 -5
arch/mips/kernel/octeon_switch.S
··· 10 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 11 * written by Carsten Langgaard, carstenl@mips.com 12 12 */ 13 + #include <asm/asm.h> 14 + #include <asm/export.h> 15 + #include <asm/asm-offsets.h> 16 + #include <asm/mipsregs.h> 17 + #include <asm/regdef.h> 18 + #include <asm/stackframe.h> 13 19 14 - #define USE_ALTERNATE_RESUME_IMPL 1 15 - .set push 16 - .set arch=mips64r2 17 - #include "r4k_switch.S" 18 - .set pop 19 20 /* 20 21 * task_struct *resume(task_struct *prev, task_struct *next, 21 22 * struct thread_info *next_ti)
+196
arch/mips/kernel/r4k_fpu.S
··· 15 15 #include <asm/asm.h> 16 16 #include <asm/asmmacro.h> 17 17 #include <asm/errno.h> 18 + #include <asm/export.h> 18 19 #include <asm/fpregdef.h> 19 20 #include <asm/mipsregs.h> 20 21 #include <asm/asm-offsets.h> ··· 34 33 PTR .ex\@, fault 35 34 .previous 36 35 .endm 36 + 37 + /* 38 + * Save a thread's fp context. 39 + */ 40 + LEAF(_save_fp) 41 + EXPORT_SYMBOL(_save_fp) 42 + #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 43 + defined(CONFIG_CPU_MIPS32_R6) 44 + mfc0 t0, CP0_STATUS 45 + #endif 46 + fpu_save_double a0 t0 t1 # clobbers t1 47 + jr ra 48 + END(_save_fp) 49 + 50 + /* 51 + * Restore a thread's fp context. 52 + */ 53 + LEAF(_restore_fp) 54 + #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 55 + defined(CONFIG_CPU_MIPS32_R6) 56 + mfc0 t0, CP0_STATUS 57 + #endif 58 + fpu_restore_double a0 t0 t1 # clobbers t1 59 + jr ra 60 + END(_restore_fp) 61 + 62 + #ifdef CONFIG_CPU_HAS_MSA 63 + 64 + /* 65 + * Save a thread's MSA vector context. 66 + */ 67 + LEAF(_save_msa) 68 + EXPORT_SYMBOL(_save_msa) 69 + msa_save_all a0 70 + jr ra 71 + END(_save_msa) 72 + 73 + /* 74 + * Restore a thread's MSA vector context. 75 + */ 76 + LEAF(_restore_msa) 77 + msa_restore_all a0 78 + jr ra 79 + END(_restore_msa) 80 + 81 + LEAF(_init_msa_upper) 82 + msa_init_all_upper 83 + jr ra 84 + END(_init_msa_upper) 85 + 86 + #endif 87 + 88 + /* 89 + * Load the FPU with signalling NANS. This bit pattern we're using has 90 + * the property that no matter whether considered as single or as double 91 + * precision represents signaling NANS. 92 + * 93 + * The value to initialize fcr31 to comes in $a0. 94 + */ 95 + 96 + .set push 97 + SET_HARDFLOAT 98 + 99 + LEAF(_init_fpu) 100 + mfc0 t0, CP0_STATUS 101 + li t1, ST0_CU1 102 + or t0, t1 103 + mtc0 t0, CP0_STATUS 104 + enable_fpu_hazard 105 + 106 + ctc1 a0, fcr31 107 + 108 + li t1, -1 # SNaN 109 + 110 + #ifdef CONFIG_64BIT 111 + sll t0, t0, 5 112 + bgez t0, 1f # 16 / 32 register mode? 113 + 114 + dmtc1 t1, $f1 115 + dmtc1 t1, $f3 116 + dmtc1 t1, $f5 117 + dmtc1 t1, $f7 118 + dmtc1 t1, $f9 119 + dmtc1 t1, $f11 120 + dmtc1 t1, $f13 121 + dmtc1 t1, $f15 122 + dmtc1 t1, $f17 123 + dmtc1 t1, $f19 124 + dmtc1 t1, $f21 125 + dmtc1 t1, $f23 126 + dmtc1 t1, $f25 127 + dmtc1 t1, $f27 128 + dmtc1 t1, $f29 129 + dmtc1 t1, $f31 130 + 1: 131 + #endif 132 + 133 + #ifdef CONFIG_CPU_MIPS32 134 + mtc1 t1, $f0 135 + mtc1 t1, $f1 136 + mtc1 t1, $f2 137 + mtc1 t1, $f3 138 + mtc1 t1, $f4 139 + mtc1 t1, $f5 140 + mtc1 t1, $f6 141 + mtc1 t1, $f7 142 + mtc1 t1, $f8 143 + mtc1 t1, $f9 144 + mtc1 t1, $f10 145 + mtc1 t1, $f11 146 + mtc1 t1, $f12 147 + mtc1 t1, $f13 148 + mtc1 t1, $f14 149 + mtc1 t1, $f15 150 + mtc1 t1, $f16 151 + mtc1 t1, $f17 152 + mtc1 t1, $f18 153 + mtc1 t1, $f19 154 + mtc1 t1, $f20 155 + mtc1 t1, $f21 156 + mtc1 t1, $f22 157 + mtc1 t1, $f23 158 + mtc1 t1, $f24 159 + mtc1 t1, $f25 160 + mtc1 t1, $f26 161 + mtc1 t1, $f27 162 + mtc1 t1, $f28 163 + mtc1 t1, $f29 164 + mtc1 t1, $f30 165 + mtc1 t1, $f31 166 + 167 + #if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) 168 + .set push 169 + .set MIPS_ISA_LEVEL_RAW 170 + .set fp=64 171 + sll t0, t0, 5 # is Status.FR set? 172 + bgez t0, 1f # no: skip setting upper 32b 173 + 174 + mthc1 t1, $f0 175 + mthc1 t1, $f1 176 + mthc1 t1, $f2 177 + mthc1 t1, $f3 178 + mthc1 t1, $f4 179 + mthc1 t1, $f5 180 + mthc1 t1, $f6 181 + mthc1 t1, $f7 182 + mthc1 t1, $f8 183 + mthc1 t1, $f9 184 + mthc1 t1, $f10 185 + mthc1 t1, $f11 186 + mthc1 t1, $f12 187 + mthc1 t1, $f13 188 + mthc1 t1, $f14 189 + mthc1 t1, $f15 190 + mthc1 t1, $f16 191 + mthc1 t1, $f17 192 + mthc1 t1, $f18 193 + mthc1 t1, $f19 194 + mthc1 t1, $f20 195 + mthc1 t1, $f21 196 + mthc1 t1, $f22 197 + mthc1 t1, $f23 198 + mthc1 t1, $f24 199 + mthc1 t1, $f25 200 + mthc1 t1, $f26 201 + mthc1 t1, $f27 202 + mthc1 t1, $f28 203 + mthc1 t1, $f29 204 + mthc1 t1, $f30 205 + mthc1 t1, $f31 206 + 1: .set pop 207 + #endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */ 208 + #else 209 + .set MIPS_ISA_ARCH_LEVEL_RAW 210 + dmtc1 t1, $f0 211 + dmtc1 t1, $f2 212 + dmtc1 t1, $f4 213 + dmtc1 t1, $f6 214 + dmtc1 t1, $f8 215 + dmtc1 t1, $f10 216 + dmtc1 t1, $f12 217 + dmtc1 t1, $f14 218 + dmtc1 t1, $f16 219 + dmtc1 t1, $f18 220 + dmtc1 t1, $f20 221 + dmtc1 t1, $f22 222 + dmtc1 t1, $f24 223 + dmtc1 t1, $f26 224 + dmtc1 t1, $f28 225 + dmtc1 t1, $f30 226 + #endif 227 + jr ra 228 + END(_init_fpu) 229 + 230 + .set pop /* SET_HARDFLOAT */ 37 231 38 232 .set noreorder 39 233
-203
arch/mips/kernel/r4k_switch.S
··· 12 12 */ 13 13 #include <asm/asm.h> 14 14 #include <asm/cachectl.h> 15 - #include <asm/export.h> 16 - #include <asm/fpregdef.h> 17 15 #include <asm/mipsregs.h> 18 16 #include <asm/asm-offsets.h> 19 17 #include <asm/regdef.h> ··· 20 22 21 23 #include <asm/asmmacro.h> 22 24 23 - /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 24 - #undef fp 25 - 26 - #ifndef USE_ALTERNATE_RESUME_IMPL 27 25 /* 28 26 * task_struct *resume(task_struct *prev, task_struct *next, 29 27 * struct thread_info *next_ti) ··· 57 63 move v0, a0 58 64 jr ra 59 65 END(resume) 60 - 61 - #endif /* USE_ALTERNATE_RESUME_IMPL */ 62 - 63 - /* 64 - * Save a thread's fp context. 65 - */ 66 - LEAF(_save_fp) 67 - EXPORT_SYMBOL(_save_fp) 68 - #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 69 - defined(CONFIG_CPU_MIPS32_R6) 70 - mfc0 t0, CP0_STATUS 71 - #endif 72 - fpu_save_double a0 t0 t1 # clobbers t1 73 - jr ra 74 - END(_save_fp) 75 - 76 - /* 77 - * Restore a thread's fp context. 78 - */ 79 - LEAF(_restore_fp) 80 - #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 81 - defined(CONFIG_CPU_MIPS32_R6) 82 - mfc0 t0, CP0_STATUS 83 - #endif 84 - fpu_restore_double a0 t0 t1 # clobbers t1 85 - jr ra 86 - END(_restore_fp) 87 - 88 - #ifdef CONFIG_CPU_HAS_MSA 89 - 90 - /* 91 - * Save a thread's MSA vector context. 92 - */ 93 - LEAF(_save_msa) 94 - EXPORT_SYMBOL(_save_msa) 95 - msa_save_all a0 96 - jr ra 97 - END(_save_msa) 98 - 99 - /* 100 - * Restore a thread's MSA vector context. 101 - */ 102 - LEAF(_restore_msa) 103 - msa_restore_all a0 104 - jr ra 105 - END(_restore_msa) 106 - 107 - LEAF(_init_msa_upper) 108 - msa_init_all_upper 109 - jr ra 110 - END(_init_msa_upper) 111 - 112 - #endif 113 - 114 - /* 115 - * Load the FPU with signalling NANS. This bit pattern we're using has 116 - * the property that no matter whether considered as single or as double 117 - * precision represents signaling NANS. 118 - * 119 - * The value to initialize fcr31 to comes in $a0. 120 - */ 121 - 122 - .set push 123 - SET_HARDFLOAT 124 - 125 - LEAF(_init_fpu) 126 - mfc0 t0, CP0_STATUS 127 - li t1, ST0_CU1 128 - or t0, t1 129 - mtc0 t0, CP0_STATUS 130 - enable_fpu_hazard 131 - 132 - ctc1 a0, fcr31 133 - 134 - li t1, -1 # SNaN 135 - 136 - #ifdef CONFIG_64BIT 137 - sll t0, t0, 5 138 - bgez t0, 1f # 16 / 32 register mode? 139 - 140 - dmtc1 t1, $f1 141 - dmtc1 t1, $f3 142 - dmtc1 t1, $f5 143 - dmtc1 t1, $f7 144 - dmtc1 t1, $f9 145 - dmtc1 t1, $f11 146 - dmtc1 t1, $f13 147 - dmtc1 t1, $f15 148 - dmtc1 t1, $f17 149 - dmtc1 t1, $f19 150 - dmtc1 t1, $f21 151 - dmtc1 t1, $f23 152 - dmtc1 t1, $f25 153 - dmtc1 t1, $f27 154 - dmtc1 t1, $f29 155 - dmtc1 t1, $f31 156 - 1: 157 - #endif 158 - 159 - #ifdef CONFIG_CPU_MIPS32 160 - mtc1 t1, $f0 161 - mtc1 t1, $f1 162 - mtc1 t1, $f2 163 - mtc1 t1, $f3 164 - mtc1 t1, $f4 165 - mtc1 t1, $f5 166 - mtc1 t1, $f6 167 - mtc1 t1, $f7 168 - mtc1 t1, $f8 169 - mtc1 t1, $f9 170 - mtc1 t1, $f10 171 - mtc1 t1, $f11 172 - mtc1 t1, $f12 173 - mtc1 t1, $f13 174 - mtc1 t1, $f14 175 - mtc1 t1, $f15 176 - mtc1 t1, $f16 177 - mtc1 t1, $f17 178 - mtc1 t1, $f18 179 - mtc1 t1, $f19 180 - mtc1 t1, $f20 181 - mtc1 t1, $f21 182 - mtc1 t1, $f22 183 - mtc1 t1, $f23 184 - mtc1 t1, $f24 185 - mtc1 t1, $f25 186 - mtc1 t1, $f26 187 - mtc1 t1, $f27 188 - mtc1 t1, $f28 189 - mtc1 t1, $f29 190 - mtc1 t1, $f30 191 - mtc1 t1, $f31 192 - 193 - #if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) 194 - .set push 195 - .set MIPS_ISA_LEVEL_RAW 196 - .set fp=64 197 - sll t0, t0, 5 # is Status.FR set? 198 - bgez t0, 1f # no: skip setting upper 32b 199 - 200 - mthc1 t1, $f0 201 - mthc1 t1, $f1 202 - mthc1 t1, $f2 203 - mthc1 t1, $f3 204 - mthc1 t1, $f4 205 - mthc1 t1, $f5 206 - mthc1 t1, $f6 207 - mthc1 t1, $f7 208 - mthc1 t1, $f8 209 - mthc1 t1, $f9 210 - mthc1 t1, $f10 211 - mthc1 t1, $f11 212 - mthc1 t1, $f12 213 - mthc1 t1, $f13 214 - mthc1 t1, $f14 215 - mthc1 t1, $f15 216 - mthc1 t1, $f16 217 - mthc1 t1, $f17 218 - mthc1 t1, $f18 219 - mthc1 t1, $f19 220 - mthc1 t1, $f20 221 - mthc1 t1, $f21 222 - mthc1 t1, $f22 223 - mthc1 t1, $f23 224 - mthc1 t1, $f24 225 - mthc1 t1, $f25 226 - mthc1 t1, $f26 227 - mthc1 t1, $f27 228 - mthc1 t1, $f28 229 - mthc1 t1, $f29 230 - mthc1 t1, $f30 231 - mthc1 t1, $f31 232 - 1: .set pop 233 - #endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */ 234 - #else 235 - .set MIPS_ISA_ARCH_LEVEL_RAW 236 - dmtc1 t1, $f0 237 - dmtc1 t1, $f2 238 - dmtc1 t1, $f4 239 - dmtc1 t1, $f6 240 - dmtc1 t1, $f8 241 - dmtc1 t1, $f10 242 - dmtc1 t1, $f12 243 - dmtc1 t1, $f14 244 - dmtc1 t1, $f16 245 - dmtc1 t1, $f18 246 - dmtc1 t1, $f20 247 - dmtc1 t1, $f22 248 - dmtc1 t1, $f24 249 - dmtc1 t1, $f26 250 - dmtc1 t1, $f28 251 - dmtc1 t1, $f30 252 - #endif 253 - jr ra 254 - END(_init_fpu) 255 - 256 - .set pop /* SET_HARDFLOAT */