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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ath9k: Add support for more WOW patterns
Newer chips like WB222, WB335 support more than
8 user-configurable patterns. This patch adds
support for it by setting up the correct HW
registers.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
authored by
Sujith Manoharan
and committed by
Kalle Valo
a28815db
6d4beca3
+56
-27
+21
-27
drivers/net/wireless/ath/ath9k/ar9003_wow.c
+21
-27
drivers/net/wireless/ath/ath9k/ar9003_wow.c
···
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if (pattern_count >= ah->wow.max_patterns)
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return -ENOSPC;
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-
REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
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+
if (pattern_count < MAX_NUM_PATTERN_LEGACY)
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+
REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count));
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+
else
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+
REG_SET_BIT(ah, AR_MAC_PCU_WOW4, BIT(pattern_count - 8));
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-
/* set the registers for pattern */
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for (i = 0; i < MAX_PATTERN_SIZE; i += 4) {
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memcpy(&pattern_val, user_pattern, 4);
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REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i),
···
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user_pattern += 4;
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}
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-
/* set the registers for mask */
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for (i = 0; i < MAX_PATTERN_MASK_SIZE; i += 4) {
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memcpy(&mask_val, user_mask, 4);
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REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val);
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user_mask += 4;
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}
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-
/* set the pattern length to be matched
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*
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* AR_WOW_LENGTH1_REG1
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-
* bit 31:24 pattern 0 length
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-
* bit 23:16 pattern 1 length
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-
* bit 15:8 pattern 2 length
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-
* bit 7:0 pattern 3 length
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-
*
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-
* AR_WOW_LENGTH1_REG2
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-
* bit 31:24 pattern 4 length
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-
* bit 23:16 pattern 5 length
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-
* bit 15:8 pattern 6 length
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-
* bit 7:0 pattern 7 length
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-
*
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-
* the below logic writes out the new
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-
* pattern length for the corresponding
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* pattern_count, while masking out the
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-
* other fields
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-
*/
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-
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-
ah->wow.wow_event_mask |= BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
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+
if (pattern_count < MAX_NUM_PATTERN_LEGACY)
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+
ah->wow.wow_event_mask |=
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+
BIT(pattern_count + AR_WOW_PAT_FOUND_SHIFT);
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+
else
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+
ah->wow.wow_event_mask2 |=
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+
BIT((pattern_count - 8) + AR_WOW_PAT_FOUND_SHIFT);
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if (pattern_count < 4) {
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-
/* Pattern 0-3 uses AR_WOW_LENGTH1 register */
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127
set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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128
AR_WOW_LEN1_SHIFT(pattern_count);
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clr = AR_WOW_LENGTH1_MASK(pattern_count);
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REG_RMW(ah, AR_WOW_LENGTH1, set, clr);
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-
} else {
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-
/* Pattern 4-7 uses AR_WOW_LENGTH2 register */
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+
} else if (pattern_count < 8) {
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set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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AR_WOW_LEN2_SHIFT(pattern_count);
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clr = AR_WOW_LENGTH2_MASK(pattern_count);
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REG_RMW(ah, AR_WOW_LENGTH2, set, clr);
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+
} else if (pattern_count < 12) {
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+
set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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+
AR_WOW_LEN3_SHIFT(pattern_count);
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+
clr = AR_WOW_LENGTH3_MASK(pattern_count);
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+
REG_RMW(ah, AR_WOW_LENGTH3, set, clr);
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+
} else if (pattern_count < MAX_NUM_PATTERN) {
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+
set = (pattern_len & AR_WOW_LENGTH_MAX) <<
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+
AR_WOW_LEN4_SHIFT(pattern_count);
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+
clr = AR_WOW_LENGTH4_MASK(pattern_count);
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+
REG_RMW(ah, AR_WOW_LENGTH4, set, clr);
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}
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return 0;
+1
drivers/net/wireless/ath/ath9k/hw.h
+1
drivers/net/wireless/ath/ath9k/hw.h
+34
drivers/net/wireless/ath/ath9k/reg_wow.h
+34
drivers/net/wireless/ath/ath9k/reg_wow.h
···
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#define AR_WOW_KEEP_ALIVE 0x827c
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#define AR_WOW_KEEP_ALIVE_DELAY 0x8288
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#define AR_WOW_PATTERN_MATCH 0x828c
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+
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+
/*
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+
* AR_WOW_LENGTH1
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+
* bit 31:24 pattern 0 length
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+
* bit 23:16 pattern 1 length
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+
* bit 15:8 pattern 2 length
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+
* bit 7:0 pattern 3 length
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+
*
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+
* AR_WOW_LENGTH2
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+
* bit 31:24 pattern 4 length
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+
* bit 23:16 pattern 5 length
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+
* bit 15:8 pattern 6 length
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+
* bit 7:0 pattern 7 length
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+
*
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+
* AR_WOW_LENGTH3
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+
* bit 31:24 pattern 8 length
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+
* bit 23:16 pattern 9 length
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+
* bit 15:8 pattern 10 length
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+
* bit 7:0 pattern 11 length
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+
*
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+
* AR_WOW_LENGTH4
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+
* bit 31:24 pattern 12 length
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+
* bit 23:16 pattern 13 length
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+
* bit 15:8 pattern 14 length
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+
* bit 7:0 pattern 15 length
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+
*/
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#define AR_WOW_LENGTH1 0x8360
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#define AR_WOW_LENGTH2 0X8364
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+
#define AR_WOW_LENGTH3 0X8380
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+
#define AR_WOW_LENGTH4 0X8384
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+
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#define AR_WOW_PATTERN_MATCH_LT_256B 0x8368
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+
#define AR_MAC_PCU_WOW4 0x8370
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#define AR_SW_WOW_CONTROL 0x20018
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#define AR_SW_WOW_ENABLE 0x1
···
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#define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i))
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#define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3)
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#define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i))
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+
#define AR_WOW_LEN3_SHIFT(_i) ((0xb - ((_i) & 0xb)) << 0x3)
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+
#define AR_WOW_LENGTH3_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN3_SHIFT(_i))
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+
#define AR_WOW_LEN4_SHIFT(_i) ((0xf - ((_i) & 0xf)) << 0x3)
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+
#define AR_WOW_LENGTH4_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN4_SHIFT(_i))
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#endif /* REG_WOW_H */