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dt-bindings: dma: Document STM32 DMA3 controller bindings
The STM32 DMA3 is a Direct Memory Access controller with different features
depending on its hardware configuration.
The channels have not the same capabilities, some have a larger FIFO, so
their performance is higher.
This patch describes STM32 DMA3 bindings, used to select a channel that
fits client requirements, and to pre-configure the channel depending on
the client needs.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20240531150712.2503554-5-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Amelie Delaunay
and committed by
Vinod Koul
a204f64d
81d09bb5
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+135
Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml
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Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 DMA3 Controller
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description: |
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The STM32 DMA3 is a direct memory access controller with different features
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depending on its hardware configuration.
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It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High
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Performance).
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Its hardware configuration registers allow to dynamically expose its features.
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GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
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GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
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Bindings are generic for these 3 STM32 DMA3 configurations.
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DMA clients connected to the STM32 DMA3 controller must use the format
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described in "#dma-cells" property description below, using a three-cell
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specifier for each channel.
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maintainers:
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- Amelie Delaunay <amelie.delaunay@foss.st.com>
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allOf:
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- $ref: /schemas/dma/dma-controller.yaml#
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properties:
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compatible:
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const: st,stm32mp25-dma3
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reg:
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maxItems: 1
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interrupts:
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minItems: 4
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maxItems: 16
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description:
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Should contain all of the per-channel DMA interrupts in ascending order
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with respect to the DMA channel index.
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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"#dma-cells":
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const: 3
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description: |
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Specifies the number of cells needed to provide DMA controller specific
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information.
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The first cell is the request line number.
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The second cell is a 32-bit mask specifying the DMA channel requirements:
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-bit 0-1: The priority level
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0x0: low priority, low weight
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0x1: low priority, mid weight
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0x2: low priority, high weight
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0x3: high priority
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-bit 4-7: The FIFO requirement for queuing source/destination transfers
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0x0: no FIFO requirement/any channel can fit
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0x2: FIFO of 8 bytes (2^2+1)
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0x4: FIFO of 32 bytes (2^4+1)
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0x6: FIFO of 128 bytes (2^6+1)
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0x7: FIFO of 256 bytes (2^7+1)
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The third cell is a 32-bit mask specifying the DMA transfer requirements:
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-bit 0: The source incrementing burst
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0x0: fixed burst
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0x1: contiguously incremented burst
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-bit 1: The source allocated port
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0x0: port 0 is allocated to the source transfer
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0x1: port 1 is allocated to the source transfer
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-bit 4: The destination incrementing burst
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0x0: fixed burst
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0x1: contiguously incremented burst
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-bit 5: The destination allocated port
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0x0: port 0 is allocated to the destination transfer
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0x1: port 1 is allocated to the destination transfer
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-bit 8: The type of hardware request
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0x0: burst
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0x1: block
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-bit 9: The control mode
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0x0: DMA controller control mode
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0x1: peripheral control mode
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-bit 12-13: The transfer complete event mode
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0x0: at block level, transfer complete event is generated at the end
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of a block
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0x2: at LLI level, the transfer complete event is generated at the end
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of the LLI transfer
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including the update of the LLI if any
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0x3: at channel level, the transfer complete event is generated at the
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end of the last LLI
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- "#dma-cells"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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dma-controller@40400000 {
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compatible = "st,stm32mp25-dma3";
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reg = <0x40400000 0x1000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc CK_BUS_HPDMA1>;
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#dma-cells = <3>;
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};
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...