MIPS: io: Add barrier after register read in readX()

While a barrier is present in the writeX() functions before the register
write, a similar barrier is missing in the readX() functions after the
register read. This could allow memory accesses following readX() to
observe stale data.

Signed-off-by: Sinan Kaya <[e-mail]>
Reported-by: Arnd Bergmann <[e-mail]>
Cc: Ralf Baechle <[e-mail]>
Cc: Paul Burton <[e-mail]>
Cc: [e-mail]
Patchwork: https://patchwork.linux-mips.org/patch/19069/
[[e-mail]: Tidy commit message]
Signed-off-by: James Hogan <[e-mail]>

arch/mips/include/asm/io.h

···
 		BUG();							\
 	}								\
 									\
+	/* prevent prefetching of coherent DMA data prematurely */	\
+	rmb();								\
 	return pfx##ioswab##bwlq(__mem, __val);				\
 }