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[ARM] 4515/1: S3C: Move uncompress code to plat-s3c
Move the uncompress.h to plat-s3c
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by Ben Dooks and committed by Russell King a14a26ac 3ec20520
+11
-131
include/asm-arm/arch-s3c2410/uncompress.h
+11
-131
include/asm-arm/arch-s3c2410/uncompress.h
···
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#ifndef __ASM_ARCH_UNCOMPRESS_H
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#define __ASM_ARCH_UNCOMPRESS_H
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typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
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/* defines for UART registers */
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#include "asm/plat-s3c/regs-serial.h"
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#include "asm/arch/regs-gpio.h"
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#include "asm/plat-s3c/regs-watchdog.h"
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-
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/map.h>
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/* working in physical space... */
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#undef S3C2410_GPIOREG
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#undef S3C2410_WDOGREG
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-
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#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
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#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
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#include <asm/plat-s3c/uncompress.h>
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/* how many bytes we allow into the FIFO at a time in FIFO mode */
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#define FIFO_MAX (14)
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#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
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static __inline__ void
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uart_wr(unsigned int reg, unsigned int val)
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static void arch_detect_cpu(void)
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{
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volatile unsigned int *ptr;
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unsigned int cpuid;
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ptr = (volatile unsigned int *)(reg + uart_base);
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*ptr = val;
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}
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static __inline__ unsigned int
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uart_rd(unsigned int reg)
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{
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volatile unsigned int *ptr;
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ptr = (volatile unsigned int *)(reg + uart_base);
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return *ptr;
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}
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/* we can deal with the case the UARTs are being run
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* in FIFO mode, so that we don't hold up our execution
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* waiting for tx to happen...
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*/
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static void putc(int ch)
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{
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int cpuid = S3C2410_GSTATUS1_2410;
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#ifndef CONFIG_CPU_S3C2400
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cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
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cpuid &= S3C2410_GSTATUS1_IDMASK;
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#endif
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if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
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int level;
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while (1) {
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level = uart_rd(S3C2410_UFSTAT);
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if (cpuid == S3C2410_GSTATUS1_2440 ||
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cpuid == S3C2410_GSTATUS1_2442) {
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level &= S3C2440_UFSTAT_TXMASK;
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level >>= S3C2440_UFSTAT_TXSHIFT;
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} else {
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level &= S3C2410_UFSTAT_TXMASK;
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level >>= S3C2410_UFSTAT_TXSHIFT;
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}
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if (level < FIFO_MAX)
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break;
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}
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if (cpuid == S3C2410_GSTATUS1_2440 ||
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cpuid == S3C2410_GSTATUS1_2442) {
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fifo_mask = S3C2440_UFSTAT_TXMASK;
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fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
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} else {
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/* not using fifos */
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while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
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barrier();
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fifo_mask = S3C2410_UFSTAT_TXMASK;
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fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
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}
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/* write byte to transmission register */
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uart_wr(S3C2410_UTXH, ch);
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}
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static inline void flush(void)
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{
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}
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#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
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/* CONFIG_S3C2410_BOOT_WATCHDOG
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*
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* Simple boot-time watchdog setup, to reboot the system if there is
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* any problem with the boot process
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*/
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#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
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#define WDOG_COUNT (0xff00)
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static inline void arch_decomp_wdog(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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}
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static void arch_decomp_wdog_start(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
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}
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#else
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#define arch_decomp_wdog_start()
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#define arch_decomp_wdog()
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#endif
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#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
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static void arch_decomp_error(const char *x)
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{
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putstr("\n\n");
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putstr(x);
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putstr("\n\n -- System resetting\n");
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__raw_writel(0x4000, S3C2410_WTDAT);
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__raw_writel(0x4000, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
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while(1);
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}
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#define arch_error arch_decomp_error
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#endif
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static void error(char *err);
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static void
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arch_decomp_setup(void)
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{
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/* we may need to setup the uart(s) here if we are not running
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* on an BAST... the BAST will have left the uarts configured
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* after calling linux.
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*/
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arch_decomp_wdog_start();
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}
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#endif /* __ASM_ARCH_UNCOMPRESS_H */
+155
include/asm-arm/plat-s3c/uncompress.h
+155
include/asm-arm/plat-s3c/uncompress.h
···
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/* linux/include/asm-arm/plat-s3c/uncompress.h
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*
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* Copyright 2003, 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C - uncompress code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_UNCOMPRESS_H
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#define __ASM_PLAT_UNCOMPRESS_H
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typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
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/* uart setup */
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static unsigned int fifo_mask;
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static unsigned int fifo_max;
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/* forward declerations */
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static void arch_detect_cpu(void);
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/* defines for UART registers */
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#include "asm/plat-s3c/regs-serial.h"
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#include "asm/plat-s3c/regs-watchdog.h"
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/* working in physical space... */
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#undef S3C2410_WDOGREG
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#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
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/* how many bytes we allow into the FIFO at a time in FIFO mode */
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#define FIFO_MAX (14)
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#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
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static __inline__ void
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uart_wr(unsigned int reg, unsigned int val)
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{
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volatile unsigned int *ptr;
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ptr = (volatile unsigned int *)(reg + uart_base);
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*ptr = val;
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}
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static __inline__ unsigned int
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uart_rd(unsigned int reg)
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{
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volatile unsigned int *ptr;
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ptr = (volatile unsigned int *)(reg + uart_base);
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return *ptr;
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}
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/* we can deal with the case the UARTs are being run
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* in FIFO mode, so that we don't hold up our execution
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* waiting for tx to happen...
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*/
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static void putc(int ch)
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{
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if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
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int level;
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while (1) {
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level = uart_rd(S3C2410_UFSTAT);
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level &= fifo_mask;
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if (level < fifo_max)
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break;
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}
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} else {
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/* not using fifos */
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while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
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barrier();
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}
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/* write byte to transmission register */
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uart_wr(S3C2410_UTXH, ch);
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}
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static inline void flush(void)
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{
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}
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#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
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/* CONFIG_S3C2410_BOOT_WATCHDOG
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*
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* Simple boot-time watchdog setup, to reboot the system if there is
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* any problem with the boot process
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*/
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#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
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#define WDOG_COUNT (0xff00)
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static inline void arch_decomp_wdog(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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}
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static void arch_decomp_wdog_start(void)
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{
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__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
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__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
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}
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#else
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#define arch_decomp_wdog_start()
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#define arch_decomp_wdog()
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#endif
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#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
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static void arch_decomp_error(const char *x)
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{
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putstr("\n\n");
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putstr(x);
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putstr("\n\n -- System resetting\n");
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__raw_writel(0x4000, S3C2410_WTDAT);
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__raw_writel(0x4000, S3C2410_WTCNT);
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__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
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while(1);
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}
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#define arch_error arch_decomp_error
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#endif
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static void error(char *err);
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static void
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arch_decomp_setup(void)
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{
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/* we may need to setup the uart(s) here if we are not running
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* on an BAST... the BAST will have left the uarts configured
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* after calling linux.
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*/
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arch_detect_cpu();
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arch_decomp_wdog_start();
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}
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#endif /* __ASM_PLAT_UNCOMPRESS_H */