tjh.dev
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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: memory-controller: st,stm32: Split off MC properties
Split st,stm32-fmc2-ebi.yaml specific properties into
st,stm32-fmc2-ebi-props.yaml, split memory-controller bus peripheral
properties into mc-peripheral-props.yaml, reference the
st,stm32-fmc2-ebi-props.yaml in mc-peripheral-props.yaml and reference
the mc-peripheral-props.yaml in micrel,ks8851.yaml.
This way, the FMC2 controller properties in Micrel KSZ8851MLL ethernet
controller node can be properly validated.
Fixes the following warning:
arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dtb: ethernet@1,0:
Unevaluated properties are not allowed ('bank-width', 'st,fmc2-ebi-cs-mux-enable', ... 'st,fmc2-ebi-cs-write-data-hold-ns' were unexpected)
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20220928181944.194808-1-marex@denx.de
[krzk: trim warning message]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
authored by
Marek Vasut
and committed by
Krzysztof Kozlowski
a11a5deb
4985a545
+184
-137
+38
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+38
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
···
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Peripheral-specific properties for a Memory Controller bus.
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description:
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Many Memory Controllers need to add properties to peripheral devices.
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They could be common properties like reg or they could be controller
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specific like delay in clock or data lines, etc. These properties need
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to be defined in the peripheral node because they are per-peripheral
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and there can be multiple peripherals attached to a controller. All
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those properties are listed here. The controller specific properties
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should go in their own separate schema that should be referenced
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from here.
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maintainers:
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- Marek Vasut <marex@denx.de>
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properties:
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reg:
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description: Bank number, base address and size of the device.
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+
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bank-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Bank width of the device, in bytes.
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enum: [1, 2, 4]
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+
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required:
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- reg
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# The controller specific properties go here.
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allOf:
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- $ref: st,stm32-fmc2-ebi-props.yaml#
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additionalProperties: true
+144
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml
+144
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi-props.yaml
···
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Peripheral properties for ST FMC2 Controller
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maintainers:
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- Christophe Kerello <christophe.kerello@foss.st.com>
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- Marek Vasut <marex@denx.de>
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properties:
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st,fmc2-ebi-cs-transaction-type:
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description: |
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Select one of the transactions type supported
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0: Asynchronous mode 1 SRAM/FRAM.
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1: Asynchronous mode 1 PSRAM.
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2: Asynchronous mode A SRAM/FRAM.
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3: Asynchronous mode A PSRAM.
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4: Asynchronous mode 2 NOR.
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5: Asynchronous mode B NOR.
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6: Asynchronous mode C NOR.
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7: Asynchronous mode D NOR.
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8: Synchronous read synchronous write PSRAM.
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9: Synchronous read asynchronous write PSRAM.
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10: Synchronous read synchronous write NOR.
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11: Synchronous read asynchronous write NOR.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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st,fmc2-ebi-cs-cclk-enable:
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description: Continuous clock enable (first bank must be configured
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in synchronous mode). The FMC_CLK is generated continuously
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during asynchronous and synchronous access. By default, the
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FMC_CLK is only generated during synchronous access.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-mux-enable:
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description: Address/Data multiplexed on databus (valid only with
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NOR and PSRAM transactions type). By default, Address/Data
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are not multiplexed.
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$ref: /schemas/types.yaml#/definitions/flag
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+
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st,fmc2-ebi-cs-buswidth:
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description: Data bus width
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 8, 16 ]
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default: 16
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st,fmc2-ebi-cs-waitpol-high:
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description: Wait signal polarity (NWAIT signal active high).
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By default, NWAIT is active low.
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$ref: /schemas/types.yaml#/definitions/flag
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+
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st,fmc2-ebi-cs-waitcfg-enable:
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description: The NWAIT signal indicates wheither the data from the
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device are valid or if a wait state must be inserted when accessing
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the device in synchronous mode. By default, the NWAIT signal is
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active one data cycle before wait state.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-wait-enable:
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description: The NWAIT signal is enabled (its level is taken into
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account after the programmed latency period to insert wait states
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if asserted). By default, the NWAIT signal is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-asyncwait-enable:
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description: The NWAIT signal is taken into account during asynchronous
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transactions. By default, the NWAIT signal is not taken into account
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during asynchronous transactions.
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$ref: /schemas/types.yaml#/definitions/flag
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+
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st,fmc2-ebi-cs-cpsize:
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description: CRAM page size. The controller splits the burst access
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when the memory page is reached. By default, no burst split when
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crossing page boundary.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 128, 256, 512, 1024 ]
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default: 0
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st,fmc2-ebi-cs-byte-lane-setup-ns:
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description: This property configures the byte lane setup timing
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defined in nanoseconds from NBLx low to Chip Select NEx low.
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st,fmc2-ebi-cs-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed read/write
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transactions.
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st,fmc2-ebi-cs-data-setup-ns:
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description: This property defines the duration of the data setup phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-bus-turnaround-ns:
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description: This property defines the delay in nanoseconds between the
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end of current read/write transaction and the next transaction.
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st,fmc2-ebi-cs-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-clk-period-ns:
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description: This property defines the FMC_CLK output signal period in
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nanoseconds.
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st,fmc2-ebi-cs-data-latency-ns:
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description: This property defines the data latency before reading or
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writing the first data in nanoseconds.
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st,fmc2-ebi-cs-write-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed write
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transactions.
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st,fmc2-ebi-cs-write-data-setup-ns:
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description: This property defines the duration of the data setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-bus-turnaround-ns:
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description: This property defines the delay between the end of current
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write transaction and the next transaction in nanoseconds.
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st,fmc2-ebi-cs-write-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-max-low-pulse-ns:
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description: This property defines the maximum chip select low pulse
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duration in nanoseconds for synchronous transactions. When this timing
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reaches 0, the controller splits the current access, toggles NE to
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allow device refresh and restarts a new access.
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additionalProperties: true
+1
-137
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+1
-137
Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
···
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patternProperties:
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"^.*@[0-4],[a-f0-9]+$":
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type: object
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-
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properties:
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reg:
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description: Bank number, base address and size of the device.
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-
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st,fmc2-ebi-cs-transaction-type:
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description: |
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Select one of the transactions type supported
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0: Asynchronous mode 1 SRAM/FRAM.
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1: Asynchronous mode 1 PSRAM.
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2: Asynchronous mode A SRAM/FRAM.
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3: Asynchronous mode A PSRAM.
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4: Asynchronous mode 2 NOR.
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5: Asynchronous mode B NOR.
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6: Asynchronous mode C NOR.
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7: Asynchronous mode D NOR.
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8: Synchronous read synchronous write PSRAM.
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9: Synchronous read asynchronous write PSRAM.
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10: Synchronous read synchronous write NOR.
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11: Synchronous read asynchronous write NOR.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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st,fmc2-ebi-cs-cclk-enable:
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description: Continuous clock enable (first bank must be configured
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in synchronous mode). The FMC_CLK is generated continuously
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during asynchronous and synchronous access. By default, the
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FMC_CLK is only generated during synchronous access.
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$ref: /schemas/types.yaml#/definitions/flag
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-
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st,fmc2-ebi-cs-mux-enable:
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description: Address/Data multiplexed on databus (valid only with
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NOR and PSRAM transactions type). By default, Address/Data
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are not multiplexed.
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$ref: /schemas/types.yaml#/definitions/flag
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-
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st,fmc2-ebi-cs-buswidth:
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description: Data bus width
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 8, 16 ]
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default: 16
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st,fmc2-ebi-cs-waitpol-high:
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description: Wait signal polarity (NWAIT signal active high).
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By default, NWAIT is active low.
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$ref: /schemas/types.yaml#/definitions/flag
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-
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st,fmc2-ebi-cs-waitcfg-enable:
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description: The NWAIT signal indicates wheither the data from the
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device are valid or if a wait state must be inserted when accessing
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the device in synchronous mode. By default, the NWAIT signal is
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active one data cycle before wait state.
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$ref: /schemas/types.yaml#/definitions/flag
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-
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st,fmc2-ebi-cs-wait-enable:
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description: The NWAIT signal is enabled (its level is taken into
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account after the programmed latency period to insert wait states
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if asserted). By default, the NWAIT signal is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-asyncwait-enable:
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description: The NWAIT signal is taken into account during asynchronous
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transactions. By default, the NWAIT signal is not taken into account
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during asynchronous transactions.
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$ref: /schemas/types.yaml#/definitions/flag
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-
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st,fmc2-ebi-cs-cpsize:
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description: CRAM page size. The controller splits the burst access
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when the memory page is reached. By default, no burst split when
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crossing page boundary.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 128, 256, 512, 1024 ]
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default: 0
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st,fmc2-ebi-cs-byte-lane-setup-ns:
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description: This property configures the byte lane setup timing
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defined in nanoseconds from NBLx low to Chip Select NEx low.
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st,fmc2-ebi-cs-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed read/write
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transactions.
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st,fmc2-ebi-cs-data-setup-ns:
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description: This property defines the duration of the data setup phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-bus-turnaround-ns:
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description: This property defines the delay in nanoseconds between the
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end of current read/write transaction and the next transaction.
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st,fmc2-ebi-cs-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-clk-period-ns:
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description: This property defines the FMC_CLK output signal period in
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nanoseconds.
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st,fmc2-ebi-cs-data-latency-ns:
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description: This property defines the data latency before reading or
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writing the first data in nanoseconds.
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st,fmc2-ebi-cs-write-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed write
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transactions.
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st,fmc2-ebi-cs-write-data-setup-ns:
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description: This property defines the duration of the data setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-bus-turnaround-ns:
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description: This property defines the delay between the end of current
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write transaction and the next transaction in nanoseconds.
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st,fmc2-ebi-cs-write-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous write transactions.
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-
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st,fmc2-ebi-cs-max-low-pulse-ns:
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description: This property defines the maximum chip select low pulse
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duration in nanoseconds for synchronous transactions. When this timing
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reaches 0, the controller splits the current access, toggles NE to
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allow device refresh and restarts a new access.
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required:
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- reg
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$ref: mc-peripheral-props.yaml#
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required:
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- "#address-cells"