tjh.dev / kernel
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PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code

Most DWC drivers use the common register resource names "dbi", "dbi2", and
"addr_space", so let's move their setup into the DWC common code.

This means 'dbi_base' in particular is setup later, but it looks like no
drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init.

Link: https://lore.kernel.org/r/20201105211159.1814485-4-robh@kernel.org
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Minghuan Lian <minghuan.Lian@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Roy Zang <roy.zang@nxp.com>
Cc: Jonathan Chocron <jonnyc@amazon.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Song <songxiaowei@hisilicon.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stanimir Varbanov <svarbanov@mm-sol.com>
Cc: Pratyush Anand <pratyush.anand@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: linux-omap@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-arm-kernel@axis.com
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org

authored by

Rob Herring and committed by
Lorenzo Pieralisi a0fd361d 1d567aac

+47 -254
-8
drivers/pci/controller/dwc/pci-dra7xx.c
··· 578 578 { 579 579 int ret; 580 580 struct dw_pcie_ep *ep; 581 - struct resource *res; 582 581 struct device *dev = &pdev->dev; 583 582 struct dw_pcie *pci = dra7xx->pci; 584 583 ··· 592 593 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2"); 593 594 if (IS_ERR(pci->dbi_base2)) 594 595 return PTR_ERR(pci->dbi_base2); 595 - 596 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 597 - if (!res) 598 - return -EINVAL; 599 - 600 - ep->phys_base = res->start; 601 - ep->addr_size = resource_size(res); 602 596 603 597 ret = dw_pcie_ep_init(ep); 604 598 if (ret) {
+1 -28
drivers/pci/controller/dwc/pci-keystone.c
··· 977 977 .get_features = &ks_pcie_am654_get_features, 978 978 }; 979 979 980 - static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, 981 - struct platform_device *pdev) 982 - { 983 - int ret; 984 - struct dw_pcie_ep *ep; 985 - struct resource *res; 986 - struct device *dev = &pdev->dev; 987 - struct dw_pcie *pci = ks_pcie->pci; 988 - 989 - ep = &pci->ep; 990 - 991 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 992 - if (!res) 993 - return -EINVAL; 994 - 995 - ep->phys_base = res->start; 996 - ep->addr_size = resource_size(res); 997 - 998 - ret = dw_pcie_ep_init(ep); 999 - if (ret) { 1000 - dev_err(dev, "failed to initialize endpoint\n"); 1001 - return ret; 1002 - } 1003 - 1004 - return 0; 1005 - } 1006 - 1007 980 static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) 1008 981 { 1009 982 int num_lanes = ks_pcie->num_lanes; ··· 1286 1313 } 1287 1314 1288 1315 pci->ep.ops = ep_ops; 1289 - ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); 1316 + ret = dw_pcie_ep_init(&pci->ep); 1290 1317 if (ret < 0) 1291 1318 goto err_get_sync; 1292 1319 break;
+2 -35
drivers/pci/controller/dwc/pci-layerscape-ep.c
··· 18 18 19 19 #include "pcie-designware.h" 20 20 21 - #define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/ 22 - 23 21 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev) 24 22 25 23 struct ls_pcie_ep_drvdata { ··· 122 124 { }, 123 125 }; 124 126 125 - static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie, 126 - struct platform_device *pdev) 127 - { 128 - struct dw_pcie *pci = pcie->pci; 129 - struct device *dev = pci->dev; 130 - struct dw_pcie_ep *ep; 131 - struct resource *res; 132 - int ret; 133 - 134 - ep = &pci->ep; 135 - ep->ops = pcie->drvdata->ops; 136 - 137 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 138 - if (!res) 139 - return -EINVAL; 140 - 141 - ep->phys_base = res->start; 142 - ep->addr_size = resource_size(res); 143 - 144 - ret = dw_pcie_ep_init(ep); 145 - if (ret) { 146 - dev_err(dev, "failed to initialize endpoint\n"); 147 - return ret; 148 - } 149 - 150 - return 0; 151 - } 152 - 153 127 static int __init ls_pcie_ep_probe(struct platform_device *pdev) 154 128 { 155 129 struct device *dev = &pdev->dev; ··· 129 159 struct ls_pcie_ep *pcie; 130 160 struct pci_epc_features *ls_epc; 131 161 struct resource *dbi_base; 132 - int ret; 133 162 134 163 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 135 164 if (!pcie) ··· 157 188 if (IS_ERR(pci->dbi_base)) 158 189 return PTR_ERR(pci->dbi_base); 159 190 160 - pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET; 191 + pci->ep.ops = &ls_pcie_ep_ops; 161 192 162 193 platform_set_drvdata(pdev, pcie); 163 194 164 - ret = ls_add_pcie_ep(pcie, pdev); 165 - 166 - return ret; 195 + return dw_pcie_ep_init(&pci->ep); 167 196 } 168 197 169 198 static struct platform_driver ls_pcie_ep_driver = {
+1 -8
drivers/pci/controller/dwc/pcie-al.c
··· 347 347 struct device *dev = &pdev->dev; 348 348 struct resource *controller_res; 349 349 struct resource *ecam_res; 350 - struct resource *dbi_res; 351 350 struct al_pcie *al_pcie; 352 351 struct dw_pcie *pci; 353 352 ··· 364 365 al_pcie->pci = pci; 365 366 al_pcie->dev = dev; 366 367 367 - dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 368 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 369 - if (IS_ERR(pci->dbi_base)) 370 - return PTR_ERR(pci->dbi_base); 371 - 372 368 ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); 373 369 if (!ecam_res) { 374 370 dev_err(dev, "couldn't find 'config' reg in DT\n"); ··· 380 386 return PTR_ERR(al_pcie->controller_base); 381 387 } 382 388 383 - dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n", 384 - dbi_res, controller_res); 389 + dev_dbg(dev, "From DT: controller_base: %pR\n", controller_res); 385 390 386 391 platform_set_drvdata(pdev, al_pcie); 387 392
+4 -39
drivers/pci/controller/dwc/pcie-artpec6.c
··· 403 403 .raise_irq = artpec6_pcie_raise_irq, 404 404 }; 405 405 406 - static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie, 407 - struct platform_device *pdev) 408 - { 409 - int ret; 410 - struct dw_pcie_ep *ep; 411 - struct resource *res; 412 - struct device *dev = &pdev->dev; 413 - struct dw_pcie *pci = artpec6_pcie->pci; 414 - 415 - ep = &pci->ep; 416 - ep->ops = &pcie_ep_ops; 417 - 418 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 419 - if (IS_ERR(pci->dbi_base2)) 420 - return PTR_ERR(pci->dbi_base2); 421 - 422 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 423 - if (!res) 424 - return -EINVAL; 425 - 426 - ep->phys_base = res->start; 427 - ep->addr_size = resource_size(res); 428 - 429 - ret = dw_pcie_ep_init(ep); 430 - if (ret) { 431 - dev_err(dev, "failed to initialize endpoint\n"); 432 - return ret; 433 - } 434 - 435 - return 0; 436 - } 437 - 438 406 static int artpec6_pcie_probe(struct platform_device *pdev) 439 407 { 440 408 struct device *dev = &pdev->dev; ··· 437 469 artpec6_pcie->variant = variant; 438 470 artpec6_pcie->mode = mode; 439 471 440 - pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); 441 - if (IS_ERR(pci->dbi_base)) 442 - return PTR_ERR(pci->dbi_base); 443 - 444 472 artpec6_pcie->phy_base = 445 473 devm_platform_ioremap_resource_byname(pdev, "phy"); 446 474 if (IS_ERR(artpec6_pcie->phy_base)) ··· 468 504 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG); 469 505 val &= ~PCIECFG_DEVICE_TYPE_MASK; 470 506 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); 471 - ret = artpec6_add_pcie_ep(artpec6_pcie, pdev); 472 - if (ret < 0) 473 - return ret; 507 + 508 + pci->ep.ops = &pcie_ep_ops; 509 + 510 + return dw_pcie_ep_init(&pci->ep); 474 511 break; 475 512 } 476 513 default:
+26 -3
drivers/pci/controller/dwc/pcie-designware-ep.c
··· 7 7 */ 8 8 9 9 #include <linux/of.h> 10 + #include <linux/platform_device.h> 10 11 11 12 #include "pcie-designware.h" 12 13 #include <linux/pci-epc.h> ··· 677 676 int ret; 678 677 void *addr; 679 678 u8 func_no; 679 + struct resource *res; 680 680 struct pci_epc *epc; 681 681 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 682 682 struct device *dev = pci->dev; 683 + struct platform_device *pdev = to_platform_device(dev); 683 684 struct device_node *np = dev->of_node; 684 685 const struct pci_epc_features *epc_features; 685 686 struct dw_pcie_ep_func *ep_func; 686 687 687 688 INIT_LIST_HEAD(&ep->func_list); 688 689 689 - if (!pci->dbi_base || !pci->dbi_base2) { 690 - dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); 691 - return -EINVAL; 690 + if (!pci->dbi_base) { 691 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 692 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 693 + if (IS_ERR(pci->dbi_base)) 694 + return PTR_ERR(pci->dbi_base); 692 695 } 696 + 697 + if (!pci->dbi_base2) { 698 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); 699 + if (!res) 700 + pci->dbi_base2 = pci->dbi_base + SZ_4K; 701 + else { 702 + pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); 703 + if (IS_ERR(pci->dbi_base2)) 704 + return PTR_ERR(pci->dbi_base2); 705 + } 706 + } 707 + 708 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 709 + if (!res) 710 + return -EINVAL; 711 + 712 + ep->phys_base = res->start; 713 + ep->addr_size = resource_size(res); 693 714 694 715 ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); 695 716 if (ret < 0) {
+7
drivers/pci/controller/dwc/pcie-designware-host.c
··· 310 310 dev_err(dev, "Missing *config* reg space\n"); 311 311 } 312 312 313 + if (!pci->dbi_base) { 314 + struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 315 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); 316 + if (IS_ERR(pci->dbi_base)) 317 + return PTR_ERR(pci->dbi_base); 318 + } 319 + 313 320 bridge = devm_pci_alloc_host_bridge(dev, 0); 314 321 if (!bridge) 315 322 return -ENOMEM;
+2 -43
drivers/pci/controller/dwc/pcie-designware-plat.c
··· 139 139 return 0; 140 140 } 141 141 142 - static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie, 143 - struct platform_device *pdev) 144 - { 145 - int ret; 146 - struct dw_pcie_ep *ep; 147 - struct resource *res; 148 - struct device *dev = &pdev->dev; 149 - struct dw_pcie *pci = dw_plat_pcie->pci; 150 - 151 - ep = &pci->ep; 152 - ep->ops = &pcie_ep_ops; 153 - 154 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 155 - if (IS_ERR(pci->dbi_base2)) 156 - return PTR_ERR(pci->dbi_base2); 157 - 158 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 159 - if (!res) 160 - return -EINVAL; 161 - 162 - ep->phys_base = res->start; 163 - ep->addr_size = resource_size(res); 164 - 165 - ret = dw_pcie_ep_init(ep); 166 - if (ret) { 167 - dev_err(dev, "Failed to initialize endpoint\n"); 168 - return ret; 169 - } 170 - return 0; 171 - } 172 - 173 142 static int dw_plat_pcie_probe(struct platform_device *pdev) 174 143 { 175 144 struct device *dev = &pdev->dev; 176 145 struct dw_plat_pcie *dw_plat_pcie; 177 146 struct dw_pcie *pci; 178 - struct resource *res; /* Resource from DT */ 179 147 int ret; 180 148 const struct of_device_id *match; 181 149 const struct dw_plat_pcie_of_data *data; ··· 170 202 dw_plat_pcie->pci = pci; 171 203 dw_plat_pcie->mode = mode; 172 204 173 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 174 - if (!res) 175 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 176 - 177 - pci->dbi_base = devm_ioremap_resource(dev, res); 178 - if (IS_ERR(pci->dbi_base)) 179 - return PTR_ERR(pci->dbi_base); 180 - 181 205 platform_set_drvdata(pdev, dw_plat_pcie); 182 206 183 207 switch (dw_plat_pcie->mode) { ··· 185 225 if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP)) 186 226 return -ENODEV; 187 227 188 - ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev); 189 - if (ret < 0) 190 - return ret; 228 + pci->ep.ops = &pcie_ep_ops; 229 + return dw_pcie_ep_init(&pci->ep); 191 230 break; 192 231 default: 193 232 dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
-4
drivers/pci/controller/dwc/pcie-intel-gw.c
··· 237 237 struct device *dev = pci->dev; 238 238 int ret; 239 239 240 - pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); 241 - if (IS_ERR(pci->dbi_base)) 242 - return PTR_ERR(pci->dbi_base); 243 - 244 240 lpp->core_clk = devm_clk_get(dev, NULL); 245 241 if (IS_ERR(lpp->core_clk)) { 246 242 ret = PTR_ERR(lpp->core_clk);
-5
drivers/pci/controller/dwc/pcie-kirin.c
··· 157 157 if (IS_ERR(kirin_pcie->phy_base)) 158 158 return PTR_ERR(kirin_pcie->phy_base); 159 159 160 - kirin_pcie->pci->dbi_base = 161 - devm_platform_ioremap_resource_byname(pdev, "dbi"); 162 - if (IS_ERR(kirin_pcie->pci->dbi_base)) 163 - return PTR_ERR(kirin_pcie->pci->dbi_base); 164 - 165 160 kirin_pcie->crgctrl = 166 161 syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl"); 167 162 if (IS_ERR(kirin_pcie->crgctrl))
-8
drivers/pci/controller/dwc/pcie-qcom.c
··· 1368 1368 static int qcom_pcie_probe(struct platform_device *pdev) 1369 1369 { 1370 1370 struct device *dev = &pdev->dev; 1371 - struct resource *res; 1372 1371 struct pcie_port *pp; 1373 1372 struct dw_pcie *pci; 1374 1373 struct qcom_pcie *pcie; ··· 1403 1404 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 1404 1405 if (IS_ERR(pcie->parf)) { 1405 1406 ret = PTR_ERR(pcie->parf); 1406 - goto err_pm_runtime_put; 1407 - } 1408 - 1409 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 1410 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); 1411 - if (IS_ERR(pci->dbi_base)) { 1412 - ret = PTR_ERR(pci->dbi_base); 1413 1407 goto err_pm_runtime_put; 1414 1408 } 1415 1409
+2 -9
drivers/pci/controller/dwc/pcie-spear13xx.c
··· 152 152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 153 153 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci); 154 154 155 + spear13xx_pcie->app_base = pci->dbi_base + 0x2000; 156 + 155 157 spear13xx_pcie_establish_link(spear13xx_pcie); 156 158 spear13xx_pcie_enable_interrupts(spear13xx_pcie); 157 159 ··· 205 203 struct dw_pcie *pci; 206 204 struct spear13xx_pcie *spear13xx_pcie; 207 205 struct device_node *np = dev->of_node; 208 - struct resource *dbi_base; 209 206 int ret; 210 207 211 208 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL); ··· 242 241 dev_err(dev, "couldn't enable clk for pcie\n"); 243 242 return ret; 244 243 } 245 - 246 - dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 247 - pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); 248 - if (IS_ERR(pci->dbi_base)) { 249 - ret = PTR_ERR(pci->dbi_base); 250 - goto fail_clk; 251 - } 252 - spear13xx_pcie->app_base = pci->dbi_base + 0x2000; 253 244 254 245 if (of_property_read_bool(np, "st,pcie-is-gen1")) 255 246 pci->link_gen = 1;
-22
drivers/pci/controller/dwc/pcie-tegra194.c
··· 1907 1907 struct dw_pcie *pci = &pcie->pci; 1908 1908 struct device *dev = pcie->dev; 1909 1909 struct dw_pcie_ep *ep; 1910 - struct resource *res; 1911 1910 char *name; 1912 1911 int ret; 1913 1912 1914 1913 ep = &pci->ep; 1915 1914 ep->ops = &pcie_ep_ops; 1916 1915 1917 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 1918 - if (!res) 1919 - return -EINVAL; 1920 - 1921 - ep->phys_base = res->start; 1922 - ep->addr_size = resource_size(res); 1923 1916 ep->page_size = SZ_64K; 1924 1917 1925 1918 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); ··· 1975 1982 struct device *dev = &pdev->dev; 1976 1983 struct resource *atu_dma_res; 1977 1984 struct tegra_pcie_dw *pcie; 1978 - struct resource *dbi_res; 1979 1985 struct pcie_port *pp; 1980 1986 struct dw_pcie *pci; 1981 1987 struct phy **phys; ··· 2082 2090 } 2083 2091 2084 2092 pcie->phys = phys; 2085 - 2086 - dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 2087 - if (!dbi_res) { 2088 - dev_err(dev, "Failed to find \"dbi\" region\n"); 2089 - return -ENODEV; 2090 - } 2091 - pcie->dbi_res = dbi_res; 2092 - 2093 - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); 2094 - if (IS_ERR(pci->dbi_base)) 2095 - return PTR_ERR(pci->dbi_base); 2096 - 2097 - /* Tegra HW locates DBI2 at a fixed offset from DBI */ 2098 - pci->dbi_base2 = pci->dbi_base + 0x1000; 2099 2093 2100 2094 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 2101 2095 "atu_dma");
+2 -36
drivers/pci/controller/dwc/pcie-uniphier-ep.c
··· 218 218 .get_features = uniphier_pcie_get_features, 219 219 }; 220 220 221 - static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv, 222 - struct platform_device *pdev) 223 - { 224 - struct dw_pcie *pci = &priv->pci; 225 - struct dw_pcie_ep *ep = &pci->ep; 226 - struct device *dev = &pdev->dev; 227 - struct resource *res; 228 - int ret; 229 - 230 - ep->ops = &uniphier_pcie_ep_ops; 231 - 232 - pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2"); 233 - if (IS_ERR(pci->dbi_base2)) 234 - return PTR_ERR(pci->dbi_base2); 235 - 236 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); 237 - if (!res) 238 - return -EINVAL; 239 - 240 - ep->phys_base = res->start; 241 - ep->addr_size = resource_size(res); 242 - 243 - ret = dw_pcie_ep_init(ep); 244 - if (ret) 245 - dev_err(dev, "Failed to initialize endpoint (%d)\n", ret); 246 - 247 - return ret; 248 - } 249 - 250 221 static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv) 251 222 { 252 223 int ret; ··· 271 300 { 272 301 struct device *dev = &pdev->dev; 273 302 struct uniphier_pcie_ep_priv *priv; 274 - struct resource *res; 275 303 int ret; 276 304 277 305 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 283 313 284 314 priv->pci.dev = dev; 285 315 priv->pci.ops = &dw_pcie_ops; 286 - 287 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 288 - priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); 289 - if (IS_ERR(priv->pci.dbi_base)) 290 - return PTR_ERR(priv->pci.dbi_base); 291 316 292 317 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); 293 318 if (IS_ERR(priv->base)) ··· 317 352 if (ret) 318 353 return ret; 319 354 320 - return uniphier_add_pcie_ep(priv, pdev); 355 + priv->pci.ep.ops = &uniphier_pcie_ep_ops; 356 + return dw_pcie_ep_init(&priv->pci.ep); 321 357 } 322 358 323 359 static const struct pci_epc_features uniphier_pro5_data = {
-6
drivers/pci/controller/dwc/pcie-uniphier.c
··· 400 400 { 401 401 struct device *dev = &pdev->dev; 402 402 struct uniphier_pcie_priv *priv; 403 - struct resource *res; 404 403 int ret; 405 404 406 405 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ··· 408 409 409 410 priv->pci.dev = dev; 410 411 priv->pci.ops = &dw_pcie_ops; 411 - 412 - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 413 - priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res); 414 - if (IS_ERR(priv->pci.dbi_base)) 415 - return PTR_ERR(priv->pci.dbi_base); 416 412 417 413 priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); 418 414 if (IS_ERR(priv->base))