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m68k: coldfire: Use proper clock rate for timers

The DMA and PIT timers are clocked at fsys/2. Fix it.
While at it, fix the comment naming for DMA timers (duplicated tmr.2).

Signed-off-by: Jean-Michel Hautbois <jeanmichel.hautbois@yoseli.org>
Signed-off-by: Greg Ungerer <gerg@kernel.org>

authored by

Jean-Michel Hautbois and committed by
Greg Ungerer a0a8306c 5bc55a33

+10 -10
+10 -10
arch/m68k/coldfire/m5441x.c
··· 33 33 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 34 34 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK); 35 35 DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK); 36 - DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK); 37 - DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK); 38 - DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK); 39 - DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK); 40 - DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK); 41 - DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK); 42 - DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK); 43 - DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK); 36 + DEFINE_CLK(0, "mcftmr.0", 28, MCF_BUSCLK); 37 + DEFINE_CLK(0, "mcftmr.1", 29, MCF_BUSCLK); 38 + DEFINE_CLK(0, "mcftmr.2", 30, MCF_BUSCLK); 39 + DEFINE_CLK(0, "mcftmr.3", 31, MCF_BUSCLK); 40 + DEFINE_CLK(0, "mcfpit.0", 32, MCF_BUSCLK); 41 + DEFINE_CLK(0, "mcfpit.1", 33, MCF_BUSCLK); 42 + DEFINE_CLK(0, "mcfpit.2", 34, MCF_BUSCLK); 43 + DEFINE_CLK(0, "mcfpit.3", 35, MCF_BUSCLK); 44 44 DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK); 45 45 DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK); 46 46 DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK); ··· 167 167 &__clk_0_14, /* i2c.1 */ 168 168 &__clk_0_22, /* i2c.0 */ 169 169 &__clk_0_23, /* dspi.0 */ 170 - &__clk_0_28, /* tmr.1 */ 171 - &__clk_0_29, /* tmr.2 */ 170 + &__clk_0_28, /* tmr.0 */ 171 + &__clk_0_29, /* tmr.1 */ 172 172 &__clk_0_30, /* tmr.2 */ 173 173 &__clk_0_31, /* tmr.3 */ 174 174 &__clk_0_32, /* pit.0 */