Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge tag 'char-misc-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc fixes from Greg KH:
"Here are two counter driver fixes that I realized I never sent to you
for 6.14-final.
They have been in my for weeks, as well as linux-next, my fault for
not sending them earlier. They are:
- bugfix for stm32-lptimer-cnt counter driver
- bugfix for microchip-tcb-capture counter driver
Again, these have been in linux-next for weeks with no reported
issues"
* tag 'char-misc-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
counter: microchip-tcb-capture: Fix undefined counter channel state on probe
counter: stm32-lptimer-cnt: fix error handling when enabling
+19
drivers/counter/microchip-tcb-capture.c
+19
drivers/counter/microchip-tcb-capture.c
···
519
channel);
520
}
521
522
+
/* Disable Quadrature Decoder and position measure */
523
+
ret = regmap_update_bits(regmap, ATMEL_TC_BMR, ATMEL_TC_QDEN | ATMEL_TC_POSEN, 0);
524
+
if (ret)
525
+
return ret;
526
+
527
+
/* Setup the period capture mode */
528
+
ret = regmap_update_bits(regmap, ATMEL_TC_REG(priv->channel[0], CMR),
529
+
ATMEL_TC_WAVE | ATMEL_TC_ABETRG | ATMEL_TC_CMR_MASK |
530
+
ATMEL_TC_TCCLKS,
531
+
ATMEL_TC_CMR_MASK);
532
+
if (ret)
533
+
return ret;
534
+
535
+
/* Enable clock and trigger counter */
536
+
ret = regmap_write(regmap, ATMEL_TC_REG(priv->channel[0], CCR),
537
+
ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
538
+
if (ret)
539
+
return ret;
540
+
541
priv->tc_cfg = tcb_config;
542
priv->regmap = regmap;
543
counter->name = dev_name(&pdev->dev);
+15
-9
drivers/counter/stm32-lptimer-cnt.c
+15
-9
drivers/counter/stm32-lptimer-cnt.c
···
58
return 0;
59
}
60
61
/* LP timer must be enabled before writing CMP & ARR */
62
ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
63
if (ret)
64
-
return ret;
65
66
ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
67
if (ret)
68
-
return ret;
69
70
/* ensure CMP & ARR registers are properly written */
71
ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
72
(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
73
100, 1000);
74
if (ret)
75
-
return ret;
76
77
ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
78
STM32_LPTIM_CMPOKCF_ARROKCF);
79
if (ret)
80
-
return ret;
81
82
-
ret = clk_enable(priv->clk);
83
-
if (ret) {
84
-
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
85
-
return ret;
86
-
}
87
priv->enabled = true;
88
89
/* Start LP timer in continuous mode */
90
return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
91
STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
92
}
93
94
static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
···
58
return 0;
59
}
60
61
+
ret = clk_enable(priv->clk);
62
+
if (ret)
63
+
goto disable_cnt;
64
+
65
/* LP timer must be enabled before writing CMP & ARR */
66
ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
67
if (ret)
68
+
goto disable_clk;
69
70
ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
71
if (ret)
72
+
goto disable_clk;
73
74
/* ensure CMP & ARR registers are properly written */
75
ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
76
(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
77
100, 1000);
78
if (ret)
79
+
goto disable_clk;
80
81
ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
82
STM32_LPTIM_CMPOKCF_ARROKCF);
83
if (ret)
84
+
goto disable_clk;
85
86
priv->enabled = true;
87
88
/* Start LP timer in continuous mode */
89
return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
90
STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
91
+
92
+
disable_clk:
93
+
clk_disable(priv->clk);
94
+
disable_cnt:
95
+
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
96
+
97
+
return ret;
98
}
99
100
static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)