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ARM: imx: clk-imx6q: AXI clock select index is incorrect

The AXI clock mux should be as below:

00: periph;
01: pll2_pfd2_396m;
10: periph;
11: pll3_pfd1_540m;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

authored by

Anson Huang and committed by
Shawn Guo
a08b9bc5 37523dc5

+1 -1
+1 -1
arch/arm/mach-imx/clk-imx6q.c
··· 181 181 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; 182 182 static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; 183 183 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; 184 - static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", }; 184 + static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; 185 185 static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; 186 186 static const char *gpu_axi_sels[] = { "axi", "ahb", }; 187 187 static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };