tjh.dev / kernel
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drm/i915/power: convert assert_chv_phy_status() to struct intel_display

struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch assert_chv_phy_status() and its
callers to it. Main motivation to do just one function is to stop
passing i915 to intel_de_wait(), so its generic wrapper can be removed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/de6b01e1f21934ff520aa3b49ab5f97cbbf028f2.1730146000.git.jani.nikula@intel.com

Jani Nikula a00d086b 6400c0b9

+50 -45
+50 -45
drivers/gpu/drm/i915/display/intel_display_power_well.c
··· 1337 1337 1338 1338 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1339 1339 1340 - static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1340 + static void assert_chv_phy_status(struct intel_display *display) 1341 1341 { 1342 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1342 1343 struct i915_power_well *cmn_bc = 1343 1344 lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1344 1345 struct i915_power_well *cmn_d = 1345 1346 lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1346 - u32 phy_control = dev_priv->display.power.chv_phy_control; 1347 + u32 phy_control = display->power.chv_phy_control; 1347 1348 u32 phy_status = 0; 1348 1349 u32 phy_status_mask = 0xffffffff; 1349 1350 ··· 1355 1354 * reset (ie. the power well has been disabled at 1356 1355 * least once). 1357 1356 */ 1358 - if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0]) 1357 + if (!display->power.chv_phy_assert[DPIO_PHY0]) 1359 1358 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1360 1359 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1361 1360 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | ··· 1363 1362 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1364 1363 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1365 1364 1366 - if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1]) 1365 + if (!display->power.chv_phy_assert[DPIO_PHY1]) 1367 1366 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1368 1367 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1369 1368 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); ··· 1391 1390 */ 1392 1391 if (BITS_SET(phy_control, 1393 1392 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1394 - (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1393 + (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1395 1394 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1396 1395 1397 1396 if (BITS_SET(phy_control, ··· 1434 1433 * The PHY may be busy with some initial calibration and whatnot, 1435 1434 * so the power state can take a while to actually change. 1436 1435 */ 1437 - if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS, 1436 + if (intel_de_wait(display, DISPLAY_PHY_STATUS, 1438 1437 phy_status_mask, phy_status, 10)) 1439 - drm_err(&dev_priv->drm, 1438 + drm_err(display->drm, 1440 1439 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1441 - intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask, 1442 - phy_status, dev_priv->display.power.chv_phy_control); 1440 + intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask, 1441 + phy_status, display->power.chv_phy_control); 1443 1442 } 1444 1443 1445 1444 #undef BITS_SET ··· 1447 1446 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1448 1447 struct i915_power_well *power_well) 1449 1448 { 1449 + struct intel_display *display = &dev_priv->display; 1450 1450 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1451 1451 enum dpio_phy phy; 1452 1452 u32 tmp; 1453 1453 1454 - drm_WARN_ON_ONCE(&dev_priv->drm, 1454 + drm_WARN_ON_ONCE(display->drm, 1455 1455 id != VLV_DISP_PW_DPIO_CMN_BC && 1456 1456 id != CHV_DISP_PW_DPIO_CMN_D); 1457 1457 ··· 1466 1464 vlv_set_power_well(dev_priv, power_well, true); 1467 1465 1468 1466 /* Poll for phypwrgood signal */ 1469 - if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, 1467 + if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, 1470 1468 PHY_POWERGOOD(phy), 1)) 1471 - drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", 1469 + drm_err(display->drm, "Display PHY %d is not power up\n", 1472 1470 phy); 1473 1471 1474 1472 vlv_dpio_get(dev_priv); ··· 1496 1494 1497 1495 vlv_dpio_put(dev_priv); 1498 1496 1499 - dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1500 - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1501 - dev_priv->display.power.chv_phy_control); 1497 + display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1498 + intel_de_write(display, DISPLAY_PHY_CONTROL, 1499 + display->power.chv_phy_control); 1502 1500 1503 - drm_dbg_kms(&dev_priv->drm, 1501 + drm_dbg_kms(display->drm, 1504 1502 "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1505 - phy, dev_priv->display.power.chv_phy_control); 1503 + phy, display->power.chv_phy_control); 1506 1504 1507 - assert_chv_phy_status(dev_priv); 1505 + assert_chv_phy_status(display); 1508 1506 } 1509 1507 1510 1508 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1511 1509 struct i915_power_well *power_well) 1512 1510 { 1511 + struct intel_display *display = &dev_priv->display; 1513 1512 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1514 1513 enum dpio_phy phy; 1515 1514 1516 - drm_WARN_ON_ONCE(&dev_priv->drm, 1515 + drm_WARN_ON_ONCE(display->drm, 1517 1516 id != VLV_DISP_PW_DPIO_CMN_BC && 1518 1517 id != CHV_DISP_PW_DPIO_CMN_D); 1519 1518 ··· 1527 1524 assert_pll_disabled(dev_priv, PIPE_C); 1528 1525 } 1529 1526 1530 - dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1531 - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1532 - dev_priv->display.power.chv_phy_control); 1527 + display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1528 + intel_de_write(display, DISPLAY_PHY_CONTROL, 1529 + display->power.chv_phy_control); 1533 1530 1534 1531 vlv_set_power_well(dev_priv, power_well, false); 1535 1532 1536 - drm_dbg_kms(&dev_priv->drm, 1533 + drm_dbg_kms(display->drm, 1537 1534 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1538 - phy, dev_priv->display.power.chv_phy_control); 1535 + phy, display->power.chv_phy_control); 1539 1536 1540 1537 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1541 - dev_priv->display.power.chv_phy_assert[phy] = true; 1538 + display->power.chv_phy_assert[phy] = true; 1542 1539 1543 - assert_chv_phy_status(dev_priv); 1540 + assert_chv_phy_status(display); 1544 1541 } 1545 1542 1546 1543 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, ··· 1610 1607 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1611 1608 enum dpio_channel ch, bool override) 1612 1609 { 1613 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1610 + struct intel_display *display = &dev_priv->display; 1611 + struct i915_power_domains *power_domains = &display->power.domains; 1614 1612 bool was_override; 1615 1613 1616 1614 mutex_lock(&power_domains->lock); 1617 1615 1618 - was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1616 + was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1619 1617 1620 1618 if (override == was_override) 1621 1619 goto out; 1622 1620 1623 1621 if (override) 1624 - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1622 + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1625 1623 else 1626 - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1624 + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1627 1625 1628 - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1629 - dev_priv->display.power.chv_phy_control); 1626 + intel_de_write(display, DISPLAY_PHY_CONTROL, 1627 + display->power.chv_phy_control); 1630 1628 1631 - drm_dbg_kms(&dev_priv->drm, 1629 + drm_dbg_kms(display->drm, 1632 1630 "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1633 - phy, ch, dev_priv->display.power.chv_phy_control); 1631 + phy, ch, display->power.chv_phy_control); 1634 1632 1635 - assert_chv_phy_status(dev_priv); 1633 + assert_chv_phy_status(display); 1636 1634 1637 1635 out: 1638 1636 mutex_unlock(&power_domains->lock); ··· 1644 1640 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1645 1641 bool override, unsigned int mask) 1646 1642 { 1643 + struct intel_display *display = to_intel_display(encoder); 1647 1644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1648 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1645 + struct i915_power_domains *power_domains = &display->power.domains; 1649 1646 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1650 1647 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 1651 1648 1652 1649 mutex_lock(&power_domains->lock); 1653 1650 1654 - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1655 - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1651 + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1652 + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1656 1653 1657 1654 if (override) 1658 - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1655 + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1659 1656 else 1660 - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1657 + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1661 1658 1662 - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1663 - dev_priv->display.power.chv_phy_control); 1659 + intel_de_write(display, DISPLAY_PHY_CONTROL, 1660 + display->power.chv_phy_control); 1664 1661 1665 - drm_dbg_kms(&dev_priv->drm, 1662 + drm_dbg_kms(display->drm, 1666 1663 "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1667 - phy, ch, mask, dev_priv->display.power.chv_phy_control); 1664 + phy, ch, mask, display->power.chv_phy_control); 1668 1665 1669 - assert_chv_phy_status(dev_priv); 1666 + assert_chv_phy_status(display); 1670 1667 1671 1668 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1672 1669