Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

tools: arm64: Grab a copy of esr.h from kernel

Grab esr.h and brk-imm.h for subsequent use in KVM selftests.

Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241025203106.3529261-3-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

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tools/arch/arm64/include/asm/brk-imm.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2012 ARM Ltd. 4 + */ 5 + 6 + #ifndef __ASM_BRK_IMM_H 7 + #define __ASM_BRK_IMM_H 8 + 9 + /* 10 + * #imm16 values used for BRK instruction generation 11 + * 0x004: for installing kprobes 12 + * 0x005: for installing uprobes 13 + * 0x006: for kprobe software single-step 14 + * 0x007: for kretprobe return 15 + * Allowed values for kgdb are 0x400 - 0x7ff 16 + * 0x100: for triggering a fault on purpose (reserved) 17 + * 0x400: for dynamic BRK instruction 18 + * 0x401: for compile time BRK instruction 19 + * 0x800: kernel-mode BUG() and WARN() traps 20 + * 0x9xx: tag-based KASAN trap (allowed values 0x900 - 0x9ff) 21 + * 0x55xx: Undefined Behavior Sanitizer traps ('U' << 8) 22 + * 0x8xxx: Control-Flow Integrity traps 23 + */ 24 + #define KPROBES_BRK_IMM 0x004 25 + #define UPROBES_BRK_IMM 0x005 26 + #define KPROBES_BRK_SS_IMM 0x006 27 + #define KRETPROBES_BRK_IMM 0x007 28 + #define FAULT_BRK_IMM 0x100 29 + #define KGDB_DYN_DBG_BRK_IMM 0x400 30 + #define KGDB_COMPILED_DBG_BRK_IMM 0x401 31 + #define BUG_BRK_IMM 0x800 32 + #define KASAN_BRK_IMM 0x900 33 + #define KASAN_BRK_MASK 0x0ff 34 + #define UBSAN_BRK_IMM 0x5500 35 + #define UBSAN_BRK_MASK 0x00ff 36 + 37 + #define CFI_BRK_IMM_TARGET GENMASK(4, 0) 38 + #define CFI_BRK_IMM_TYPE GENMASK(9, 5) 39 + #define CFI_BRK_IMM_BASE 0x8000 40 + #define CFI_BRK_IMM_MASK (CFI_BRK_IMM_TARGET | CFI_BRK_IMM_TYPE) 41 + 42 + #endif
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tools/arch/arm64/include/asm/esr.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (C) 2013 - ARM Ltd 4 + * Author: Marc Zyngier <marc.zyngier@arm.com> 5 + */ 6 + 7 + #ifndef __ASM_ESR_H 8 + #define __ASM_ESR_H 9 + 10 + #include <asm/sysreg.h> 11 + 12 + #define ESR_ELx_EC_UNKNOWN UL(0x00) 13 + #define ESR_ELx_EC_WFx UL(0x01) 14 + /* Unallocated EC: 0x02 */ 15 + #define ESR_ELx_EC_CP15_32 UL(0x03) 16 + #define ESR_ELx_EC_CP15_64 UL(0x04) 17 + #define ESR_ELx_EC_CP14_MR UL(0x05) 18 + #define ESR_ELx_EC_CP14_LS UL(0x06) 19 + #define ESR_ELx_EC_FP_ASIMD UL(0x07) 20 + #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ 21 + #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ 22 + /* Unallocated EC: 0x0A - 0x0B */ 23 + #define ESR_ELx_EC_CP14_64 UL(0x0C) 24 + #define ESR_ELx_EC_BTI UL(0x0D) 25 + #define ESR_ELx_EC_ILL UL(0x0E) 26 + /* Unallocated EC: 0x0F - 0x10 */ 27 + #define ESR_ELx_EC_SVC32 UL(0x11) 28 + #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */ 29 + #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */ 30 + /* Unallocated EC: 0x14 */ 31 + #define ESR_ELx_EC_SVC64 UL(0x15) 32 + #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */ 33 + #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */ 34 + #define ESR_ELx_EC_SYS64 UL(0x18) 35 + #define ESR_ELx_EC_SVE UL(0x19) 36 + #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */ 37 + /* Unallocated EC: 0x1B */ 38 + #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */ 39 + #define ESR_ELx_EC_SME UL(0x1D) 40 + /* Unallocated EC: 0x1E */ 41 + #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */ 42 + #define ESR_ELx_EC_IABT_LOW UL(0x20) 43 + #define ESR_ELx_EC_IABT_CUR UL(0x21) 44 + #define ESR_ELx_EC_PC_ALIGN UL(0x22) 45 + /* Unallocated EC: 0x23 */ 46 + #define ESR_ELx_EC_DABT_LOW UL(0x24) 47 + #define ESR_ELx_EC_DABT_CUR UL(0x25) 48 + #define ESR_ELx_EC_SP_ALIGN UL(0x26) 49 + #define ESR_ELx_EC_MOPS UL(0x27) 50 + #define ESR_ELx_EC_FP_EXC32 UL(0x28) 51 + /* Unallocated EC: 0x29 - 0x2B */ 52 + #define ESR_ELx_EC_FP_EXC64 UL(0x2C) 53 + /* Unallocated EC: 0x2D - 0x2E */ 54 + #define ESR_ELx_EC_SERROR UL(0x2F) 55 + #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) 56 + #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) 57 + #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32) 58 + #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33) 59 + #define ESR_ELx_EC_WATCHPT_LOW UL(0x34) 60 + #define ESR_ELx_EC_WATCHPT_CUR UL(0x35) 61 + /* Unallocated EC: 0x36 - 0x37 */ 62 + #define ESR_ELx_EC_BKPT32 UL(0x38) 63 + /* Unallocated EC: 0x39 */ 64 + #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */ 65 + /* Unallocated EC: 0x3B */ 66 + #define ESR_ELx_EC_BRK64 UL(0x3C) 67 + /* Unallocated EC: 0x3D - 0x3F */ 68 + #define ESR_ELx_EC_MAX UL(0x3F) 69 + 70 + #define ESR_ELx_EC_SHIFT (26) 71 + #define ESR_ELx_EC_WIDTH (6) 72 + #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 73 + #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 74 + 75 + #define ESR_ELx_IL_SHIFT (25) 76 + #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 77 + #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) 78 + #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 79 + #define ESR_ELx_ISS2_SHIFT (32) 80 + #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) 81 + #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) 82 + 83 + /* ISS field definitions shared by different classes */ 84 + #define ESR_ELx_WNR_SHIFT (6) 85 + #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 86 + 87 + /* Asynchronous Error Type */ 88 + #define ESR_ELx_IDS_SHIFT (24) 89 + #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 90 + #define ESR_ELx_AET_SHIFT (10) 91 + #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 92 + 93 + #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 94 + #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 95 + #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 96 + #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 97 + #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 98 + 99 + /* Shared ISS field definitions for Data/Instruction aborts */ 100 + #define ESR_ELx_SET_SHIFT (11) 101 + #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 102 + #define ESR_ELx_FnV_SHIFT (10) 103 + #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 104 + #define ESR_ELx_EA_SHIFT (9) 105 + #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 106 + #define ESR_ELx_S1PTW_SHIFT (7) 107 + #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 108 + 109 + /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 110 + #define ESR_ELx_FSC (0x3F) 111 + #define ESR_ELx_FSC_TYPE (0x3C) 112 + #define ESR_ELx_FSC_LEVEL (0x03) 113 + #define ESR_ELx_FSC_EXTABT (0x10) 114 + #define ESR_ELx_FSC_MTE (0x11) 115 + #define ESR_ELx_FSC_SERROR (0x11) 116 + #define ESR_ELx_FSC_ACCESS (0x08) 117 + #define ESR_ELx_FSC_FAULT (0x04) 118 + #define ESR_ELx_FSC_PERM (0x0C) 119 + #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) 120 + #define ESR_ELx_FSC_SECC (0x18) 121 + #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) 122 + 123 + /* Status codes for individual page table levels */ 124 + #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) 125 + #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n)) 126 + 127 + #define ESR_ELx_FSC_FAULT_nL (0x2C) 128 + #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ 129 + ESR_ELx_FSC_FAULT) + (n)) 130 + 131 + /* ISS field definitions for Data Aborts */ 132 + #define ESR_ELx_ISV_SHIFT (24) 133 + #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 134 + #define ESR_ELx_SAS_SHIFT (22) 135 + #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 136 + #define ESR_ELx_SSE_SHIFT (21) 137 + #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 138 + #define ESR_ELx_SRT_SHIFT (16) 139 + #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 140 + #define ESR_ELx_SF_SHIFT (15) 141 + #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 142 + #define ESR_ELx_AR_SHIFT (14) 143 + #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 144 + #define ESR_ELx_CM_SHIFT (8) 145 + #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 146 + 147 + /* ISS2 field definitions for Data Aborts */ 148 + #define ESR_ELx_TnD_SHIFT (10) 149 + #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) 150 + #define ESR_ELx_TagAccess_SHIFT (9) 151 + #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) 152 + #define ESR_ELx_GCS_SHIFT (8) 153 + #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) 154 + #define ESR_ELx_Overlay_SHIFT (6) 155 + #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) 156 + #define ESR_ELx_DirtyBit_SHIFT (5) 157 + #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) 158 + #define ESR_ELx_Xs_SHIFT (0) 159 + #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) 160 + 161 + /* ISS field definitions for exceptions taken in to Hyp */ 162 + #define ESR_ELx_FSC_ADDRSZ (0x00) 163 + #define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n)) 164 + #define ESR_ELx_CV (UL(1) << 24) 165 + #define ESR_ELx_COND_SHIFT (20) 166 + #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 167 + #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 168 + #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 169 + #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 170 + #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 171 + #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 172 + #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 173 + #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 174 + 175 + #define DISR_EL1_IDS (UL(1) << 24) 176 + /* 177 + * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 178 + * different things in the future... 179 + */ 180 + #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 181 + 182 + /* ESR value templates for specific events */ 183 + #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 184 + (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 185 + #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 186 + ESR_ELx_WFx_ISS_WFI) 187 + 188 + /* BRK instruction trap from AArch64 state */ 189 + #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 190 + 191 + /* ISS field definitions for System instruction traps */ 192 + #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 193 + #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 194 + #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 195 + #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 196 + #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 197 + 198 + #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 199 + #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 200 + #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 201 + #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 202 + #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 203 + #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 204 + #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 205 + #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 206 + #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 207 + #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 208 + #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 209 + #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 210 + #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 211 + ESR_ELx_SYS64_ISS_OP1_MASK | \ 212 + ESR_ELx_SYS64_ISS_OP2_MASK | \ 213 + ESR_ELx_SYS64_ISS_CRN_MASK | \ 214 + ESR_ELx_SYS64_ISS_CRM_MASK) 215 + #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 216 + (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 217 + ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 218 + ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 219 + ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 220 + ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 221 + 222 + #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 223 + ESR_ELx_SYS64_ISS_DIR_MASK) 224 + #define ESR_ELx_SYS64_ISS_RT(esr) \ 225 + (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 226 + /* 227 + * User space cache operations have the following sysreg encoding 228 + * in System instructions. 229 + * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 230 + */ 231 + #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 232 + #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 233 + #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 234 + #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 235 + #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 236 + #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 237 + 238 + #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 239 + ESR_ELx_SYS64_ISS_OP1_MASK | \ 240 + ESR_ELx_SYS64_ISS_OP2_MASK | \ 241 + ESR_ELx_SYS64_ISS_CRN_MASK | \ 242 + ESR_ELx_SYS64_ISS_DIR_MASK) 243 + #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 244 + (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 245 + ESR_ELx_SYS64_ISS_DIR_WRITE) 246 + /* 247 + * User space MRS operations which are supported for emulation 248 + * have the following sysreg encoding in System instructions. 249 + * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 250 + */ 251 + #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 252 + ESR_ELx_SYS64_ISS_OP1_MASK | \ 253 + ESR_ELx_SYS64_ISS_CRN_MASK | \ 254 + ESR_ELx_SYS64_ISS_DIR_MASK) 255 + #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 256 + (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 257 + ESR_ELx_SYS64_ISS_DIR_READ) 258 + 259 + #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 260 + #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 261 + ESR_ELx_SYS64_ISS_DIR_READ) 262 + 263 + #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 264 + ESR_ELx_SYS64_ISS_DIR_READ) 265 + 266 + #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 267 + ESR_ELx_SYS64_ISS_DIR_READ) 268 + 269 + #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 270 + ESR_ELx_SYS64_ISS_DIR_READ) 271 + 272 + #define esr_sys64_to_sysreg(e) \ 273 + sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 274 + ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 275 + (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 276 + ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 277 + (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 278 + ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 279 + (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 280 + ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 281 + (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 282 + ESR_ELx_SYS64_ISS_OP2_SHIFT)) 283 + 284 + #define esr_cp15_to_sysreg(e) \ 285 + sys_reg(3, \ 286 + (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 287 + ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 288 + (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 289 + ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 290 + (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 291 + ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 292 + (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 293 + ESR_ELx_SYS64_ISS_OP2_SHIFT)) 294 + 295 + /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ 296 + #define ESR_ELx_ERET_ISS_ERET 0x2 297 + #define ESR_ELx_ERET_ISS_ERETA 0x1 298 + 299 + /* 300 + * ISS field definitions for floating-point exception traps 301 + * (FP_EXC_32/FP_EXC_64). 302 + * 303 + * (The FPEXC_* constants are used instead for common bits.) 304 + */ 305 + 306 + #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 307 + 308 + /* 309 + * ISS field definitions for CP15 accesses 310 + */ 311 + #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 312 + #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 313 + #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 314 + 315 + #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 316 + #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 317 + #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 318 + #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 319 + #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 320 + #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 321 + #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 322 + #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 323 + #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 324 + #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 325 + 326 + #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 327 + ESR_ELx_CP15_32_ISS_OP2_MASK | \ 328 + ESR_ELx_CP15_32_ISS_CRN_MASK | \ 329 + ESR_ELx_CP15_32_ISS_CRM_MASK | \ 330 + ESR_ELx_CP15_32_ISS_DIR_MASK) 331 + #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 332 + (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 333 + ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 334 + ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 335 + ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 336 + 337 + #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 338 + #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 339 + #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 340 + 341 + #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 342 + #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 343 + 344 + #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 345 + #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 346 + 347 + #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 348 + #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 349 + #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 350 + #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 351 + 352 + #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 353 + (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 354 + ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 355 + 356 + #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 357 + ESR_ELx_CP15_64_ISS_CRM_MASK | \ 358 + ESR_ELx_CP15_64_ISS_DIR_MASK) 359 + 360 + #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 361 + ESR_ELx_CP15_64_ISS_DIR_READ) 362 + 363 + #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 364 + ESR_ELx_CP15_64_ISS_DIR_READ) 365 + 366 + #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 367 + ESR_ELx_CP15_32_ISS_DIR_READ) 368 + 369 + /* 370 + * ISS values for SME traps 371 + */ 372 + 373 + #define ESR_ELx_SME_ISS_SME_DISABLED 0 374 + #define ESR_ELx_SME_ISS_ILL 1 375 + #define ESR_ELx_SME_ISS_SM_DISABLED 2 376 + #define ESR_ELx_SME_ISS_ZA_DISABLED 3 377 + #define ESR_ELx_SME_ISS_ZT_DISABLED 4 378 + 379 + /* ISS field definitions for MOPS exceptions */ 380 + #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) 381 + #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) 382 + #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) 383 + #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) 384 + #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) 385 + #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) 386 + #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) 387 + 388 + #ifndef __ASSEMBLY__ 389 + #include <asm/types.h> 390 + 391 + static inline unsigned long esr_brk_comment(unsigned long esr) 392 + { 393 + return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; 394 + } 395 + 396 + static inline bool esr_is_data_abort(unsigned long esr) 397 + { 398 + const unsigned long ec = ESR_ELx_EC(esr); 399 + 400 + return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 401 + } 402 + 403 + static inline bool esr_is_cfi_brk(unsigned long esr) 404 + { 405 + return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && 406 + (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE; 407 + } 408 + 409 + static inline bool esr_fsc_is_translation_fault(unsigned long esr) 410 + { 411 + esr = esr & ESR_ELx_FSC; 412 + 413 + return (esr == ESR_ELx_FSC_FAULT_L(3)) || 414 + (esr == ESR_ELx_FSC_FAULT_L(2)) || 415 + (esr == ESR_ELx_FSC_FAULT_L(1)) || 416 + (esr == ESR_ELx_FSC_FAULT_L(0)) || 417 + (esr == ESR_ELx_FSC_FAULT_L(-1)); 418 + } 419 + 420 + static inline bool esr_fsc_is_permission_fault(unsigned long esr) 421 + { 422 + esr = esr & ESR_ELx_FSC; 423 + 424 + return (esr == ESR_ELx_FSC_PERM_L(3)) || 425 + (esr == ESR_ELx_FSC_PERM_L(2)) || 426 + (esr == ESR_ELx_FSC_PERM_L(1)) || 427 + (esr == ESR_ELx_FSC_PERM_L(0)); 428 + } 429 + 430 + static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) 431 + { 432 + esr = esr & ESR_ELx_FSC; 433 + 434 + return (esr == ESR_ELx_FSC_ACCESS_L(3)) || 435 + (esr == ESR_ELx_FSC_ACCESS_L(2)) || 436 + (esr == ESR_ELx_FSC_ACCESS_L(1)) || 437 + (esr == ESR_ELx_FSC_ACCESS_L(0)); 438 + } 439 + 440 + /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ 441 + static inline bool esr_iss_is_eretax(unsigned long esr) 442 + { 443 + return esr & ESR_ELx_ERET_ISS_ERET; 444 + } 445 + 446 + /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ 447 + static inline bool esr_iss_is_eretab(unsigned long esr) 448 + { 449 + return esr & ESR_ELx_ERET_ISS_ERETA; 450 + } 451 + 452 + const char *esr_get_class_string(unsigned long esr); 453 + #endif /* __ASSEMBLY */ 454 + 455 + #endif /* __ASM_ESR_H */