clk: samsung: exynos7: add clocks for audio block

+9

Documentation/devicetree/bindings/clock/exynos7-clock.txt

··· 35 35 - "samsung,exynos7-clock-fsys0" 36 36 - "samsung,exynos7-clock-fsys1" 37 37 - "samsung,exynos7-clock-mscl" 38 + - "samsung,exynos7-clock-aud" 38 39 39 40 - reg: physical base address of the controller and the length of 40 41 memory mapped region. ··· 55 54 - dout_sclk_bus1_pll 56 55 - dout_sclk_cc_pll 57 56 - dout_sclk_mfc_pll 57 + - dout_sclk_aud_pll 58 58 59 59 Input clocks for top1 clock controller: 60 60 - fin_pll ··· 84 82 - sclk_spi2 85 83 - sclk_spi3 86 84 - sclk_spi4 85 + - sclk_i2s1 86 + - sclk_pcm1 87 + - sclk_spdif 87 88 88 89 Input clocks for peris clock controller: 89 90 - fin_pll ··· 102 97 - dout_aclk_fsys1_200 103 98 - dout_sclk_mmc0 104 99 - dout_sclk_mmc1 100 + 101 + Input clocks for aud clock controller: 102 + - fin_pll 103 + - fout_aud_pll

+141 -2

drivers/clk/samsung/clk-exynos7.c

··· 46 46 }; 47 47 48 48 /* List of parent clocks for Muxes in CMU_TOPC */ 49 + PNAME(mout_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 49 50 PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 50 51 PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 51 52 PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; ··· 106 105 107 106 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p, 108 107 MUX_SEL_TOPC1, 16, 1), 108 + MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1), 109 109 110 110 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 111 111 ··· 131 129 DIV_TOPC3, 12, 3), 132 130 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl", 133 131 DIV_TOPC3, 16, 3), 132 + DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl", 133 + DIV_TOPC3, 28, 3), 134 + }; 135 + 136 + static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = { 137 + PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 138 + {}, 134 139 }; 135 140 136 141 static struct samsung_gate_clock topc_gate_clks[] __initdata = { ··· 154 145 BUS1_DPLL_CON0, NULL), 155 146 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 156 147 MFC_PLL_CON0, NULL), 157 - PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 158 - AUD_PLL_CON0, NULL), 148 + PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 149 + AUD_PLL_CON0, pll1460x_24mhz_tbl), 159 150 }; 160 151 161 152 static struct samsung_cmu_info topc_cmu_info __initdata = { ··· 186 177 #define MUX_SEL_TOP00 0x0200 187 178 #define MUX_SEL_TOP01 0x0204 188 179 #define MUX_SEL_TOP03 0x020C 180 + #define MUX_SEL_TOP0_PERIC0 0x0230 189 181 #define MUX_SEL_TOP0_PERIC1 0x0234 190 182 #define MUX_SEL_TOP0_PERIC2 0x0238 191 183 #define MUX_SEL_TOP0_PERIC3 0x023C 192 184 #define DIV_TOP03 0x060C 185 + #define DIV_TOP0_PERIC0 0x0630 193 186 #define DIV_TOP0_PERIC1 0x0634 194 187 #define DIV_TOP0_PERIC2 0x0638 195 188 #define DIV_TOP0_PERIC3 0x063C 189 + #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 196 190 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 197 191 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 198 192 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C ··· 205 193 PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" }; 206 194 PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" }; 207 195 PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" }; 196 + PNAME(mout_aud_pll_p) = { "fin_pll", "dout_sclk_aud_pll" }; 208 197 209 198 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll", 210 199 "ffac_top0_bus0_pll_div2"}; ··· 219 206 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll", 220 207 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll", 221 208 "mout_top0_half_mfc_pll"}; 209 + PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 210 + "ioclk_audiocdclk1", "ioclk_spdif_extclk", 211 + "mout_top0_aud_pll", "mout_top0_half_bus0_pll", 212 + "mout_top0_half_bus1_pll"}; 213 + PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll", 214 + "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"}; 222 215 223 216 static unsigned long top0_clk_regs[] __initdata = { 224 217 MUX_SEL_TOP00, 225 218 MUX_SEL_TOP01, 226 219 MUX_SEL_TOP03, 220 + MUX_SEL_TOP0_PERIC0, 227 221 MUX_SEL_TOP0_PERIC1, 228 222 MUX_SEL_TOP0_PERIC2, 229 223 MUX_SEL_TOP0_PERIC3, 230 224 DIV_TOP03, 225 + DIV_TOP0_PERIC0, 231 226 DIV_TOP0_PERIC1, 232 227 DIV_TOP0_PERIC2, 233 228 DIV_TOP0_PERIC3, 229 + ENABLE_SCLK_TOP0_PERIC0, 234 230 ENABLE_SCLK_TOP0_PERIC1, 235 231 ENABLE_SCLK_TOP0_PERIC2, 236 232 ENABLE_SCLK_TOP0_PERIC3, 237 233 }; 238 234 239 235 static struct samsung_mux_clock top0_mux_clks[] __initdata = { 236 + MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1), 240 237 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1), 241 238 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1), 242 239 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1), ··· 263 240 264 241 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 265 242 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 243 + 244 + MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 245 + MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 246 + MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 266 247 267 248 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 268 249 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), ··· 286 259 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 287 260 DIV_TOP03, 20, 6), 288 261 262 + DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 263 + DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 264 + DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 265 + 289 266 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 290 267 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 291 268 ··· 304 273 }; 305 274 306 275 static struct samsung_gate_clock top0_gate_clks[] __initdata = { 276 + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 277 + ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 278 + GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 279 + ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 280 + GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 281 + ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 282 + 307 283 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 308 284 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 309 285 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", ··· 680 642 ENABLE_PCLK_PERIC1, 15, 0, 0), 681 643 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 682 644 ENABLE_PCLK_PERIC1, 16, 0, 0), 645 + GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 646 + ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 647 + GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 648 + ENABLE_PCLK_PERIC1, 18, 0, 0), 649 + GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 650 + ENABLE_PCLK_PERIC1, 19, 0, 0), 683 651 684 652 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 685 653 ENABLE_SCLK_PERIC10, 9, 0, 0), ··· 703 659 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 704 660 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 705 661 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 662 + GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 663 + ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 664 + GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 665 + ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 666 + GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 667 + ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 706 668 }; 707 669 708 670 static struct samsung_cmu_info peric1_cmu_info __initdata = { ··· 1056 1006 1057 1007 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1058 1008 exynos7_clk_mscl_init); 1009 + 1010 + /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1011 + #define MUX_SEL_AUD 0x0200 1012 + #define DIV_AUD0 0x0600 1013 + #define DIV_AUD1 0x0604 1014 + #define ENABLE_ACLK_AUD 0x0800 1015 + #define ENABLE_PCLK_AUD 0x0900 1016 + #define ENABLE_SCLK_AUD 0x0A00 1017 + 1018 + /* 1019 + * List of parent clocks for Muxes in CMU_AUD 1020 + */ 1021 + PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1022 + PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1023 + 1024 + static unsigned long aud_clk_regs[] __initdata = { 1025 + MUX_SEL_AUD, 1026 + DIV_AUD0, 1027 + DIV_AUD1, 1028 + ENABLE_ACLK_AUD, 1029 + ENABLE_PCLK_AUD, 1030 + ENABLE_SCLK_AUD, 1031 + }; 1032 + 1033 + static struct samsung_mux_clock aud_mux_clks[] __initdata = { 1034 + MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1035 + MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1036 + MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1037 + }; 1038 + 1039 + static struct samsung_div_clock aud_div_clks[] __initdata = { 1040 + DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1041 + DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1042 + DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1043 + 1044 + DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1045 + DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1046 + DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1047 + DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1048 + DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1049 + }; 1050 + 1051 + static struct samsung_gate_clock aud_gate_clks[] __initdata = { 1052 + GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1053 + ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1054 + GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1055 + ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1056 + GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1057 + GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1058 + ENABLE_SCLK_AUD, 30, 0, 0), 1059 + 1060 + GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1061 + GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1062 + GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1063 + GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1064 + GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1065 + GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1066 + GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1067 + ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1068 + GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1069 + ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1070 + GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1071 + GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1072 + 1073 + GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1074 + GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1075 + ENABLE_ACLK_AUD, 28, 0, 0), 1076 + GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1077 + }; 1078 + 1079 + static struct samsung_cmu_info aud_cmu_info __initdata = { 1080 + .mux_clks = aud_mux_clks, 1081 + .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1082 + .div_clks = aud_div_clks, 1083 + .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1084 + .gate_clks = aud_gate_clks, 1085 + .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1086 + .nr_clk_ids = AUD_NR_CLK, 1087 + .clk_regs = aud_clk_regs, 1088 + .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1089 + }; 1090 + 1091 + static void __init exynos7_clk_aud_init(struct device_node *np) 1092 + { 1093 + samsung_cmu_register_one(np, &aud_cmu_info); 1094 + } 1095 + 1096 + CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1097 + exynos7_clk_aud_init);

+21 -3

include/dt-bindings/clock/exynos7-clk.h

··· 19 19 #define DOUT_ACLK_CCORE_133 6 20 20 #define DOUT_ACLK_MSCL_532 7 21 21 #define ACLK_MSCL_532 8 22 - #define TOPC_NR_CLK 9 22 + #define DOUT_SCLK_AUD_PLL 9 23 + #define FOUT_AUD_PLL 10 24 + #define TOPC_NR_CLK 11 23 25 24 26 /* TOP0 */ 25 27 #define DOUT_ACLK_PERIC1 1 ··· 35 33 #define CLK_SCLK_SPI2 9 36 34 #define CLK_SCLK_SPI3 10 37 35 #define CLK_SCLK_SPI4 11 38 - #define TOP0_NR_CLK 12 36 + #define CLK_SCLK_SPDIF 12 37 + #define CLK_SCLK_PCM1 13 38 + #define CLK_SCLK_I2S1 14 39 + #define TOP0_NR_CLK 15 39 40 40 41 /* TOP1 */ 41 42 #define DOUT_ACLK_FSYS1_200 1 ··· 92 87 #define SCLK_SPI2 19 93 88 #define SCLK_SPI3 20 94 89 #define SCLK_SPI4 21 95 - #define PERIC1_NR_CLK 22 90 + #define PCLK_I2S1 22 91 + #define PCLK_PCM1 23 92 + #define PCLK_SPDIF 24 93 + #define SCLK_I2S1 25 94 + #define SCLK_PCM1 26 95 + #define SCLK_SPDIF 27 96 + #define PERIC1_NR_CLK 28 96 97 97 98 /* PERIS */ 98 99 #define PCLK_CHIPID 1 ··· 162 151 #define PCLK_PMU_MSCL 32 163 152 #define MSCL_NR_CLK 33 164 153 154 + /* AUD */ 155 + #define SCLK_I2S 1 156 + #define SCLK_PCM 2 157 + #define PCLK_I2S 3 158 + #define PCLK_PCM 4 159 + #define ACLK_ADMA 5 160 + #define AUD_NR_CLK 6 165 161 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */