Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Improve SPI support for Ingenic SoCs.

Merge series from 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:

1.Add support for using GPIOs as chip select lines on Ingenic SoCs.
2.Add support for probing the spi-ingenic driver on the JZ4775 SoC,
the X1000 SoC, and the X2000 SoC.
3.Modify annotation texts to be more in line with the current state.

+47 -7
+3
Documentation/devicetree/bindings/spi/ingenic,spi.yaml
··· 18 18 oneOf: 19 19 - enum: 20 20 - ingenic,jz4750-spi 21 + - ingenic,jz4775-spi 21 22 - ingenic,jz4780-spi 23 + - ingenic,x1000-spi 24 + - ingenic,x2000-spi 22 25 - items: 23 26 - enum: 24 27 - ingenic,jz4760-spi
+2 -2
drivers/spi/Kconfig
··· 419 419 This enables support for the Freescale i.MX SPI controllers. 420 420 421 421 config SPI_INGENIC 422 - tristate "Ingenic JZ47xx SoCs SPI controller" 422 + tristate "Ingenic SoCs SPI controller" 423 423 depends on MACH_INGENIC || COMPILE_TEST 424 424 help 425 - This enables support for the Ingenic JZ47xx SoCs SPI controller. 425 + This enables support for the Ingenic SoCs SPI controller. 426 426 427 427 To compile this driver as a module, choose M here: the module 428 428 will be called spi-ingenic.
+42 -5
drivers/spi/spi-ingenic.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* 3 - * SPI bus driver for the Ingenic JZ47xx SoCs 3 + * SPI bus driver for the Ingenic SoCs 4 4 * Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu> 5 5 * Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net> 6 + * Copyright (c) 2022 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 6 7 */ 7 8 8 9 #include <linux/clk.h> ··· 53 52 u32 bits_per_word_mask; 54 53 struct reg_field flen_field; 55 54 bool has_trendian; 55 + 56 + unsigned int max_speed_hz; 57 + unsigned int max_native_cs; 56 58 }; 57 59 58 60 struct ingenic_spi { ··· 384 380 struct spi_controller *ctlr; 385 381 struct ingenic_spi *priv; 386 382 void __iomem *base; 387 - int ret; 383 + int num_cs, ret; 388 384 389 385 pdata = of_device_get_match_data(dev); 390 386 if (!pdata) { ··· 420 416 if (IS_ERR(priv->flen_field)) 421 417 return PTR_ERR(priv->flen_field); 422 418 419 + if (device_property_read_u32(dev, "num-cs", &num_cs)) 420 + num_cs = pdata->max_native_cs; 421 + 423 422 platform_set_drvdata(pdev, ctlr); 424 423 425 424 ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware; ··· 435 428 ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE; 436 429 ctlr->bits_per_word_mask = pdata->bits_per_word_mask; 437 430 ctlr->min_speed_hz = 7200; 438 - ctlr->max_speed_hz = 54000000; 439 - ctlr->num_chipselect = 2; 431 + ctlr->max_speed_hz = pdata->max_speed_hz; 432 + ctlr->use_gpio_descriptors = true; 433 + ctlr->max_native_cs = pdata->max_native_cs; 434 + ctlr->num_chipselect = num_cs; 440 435 ctlr->dev.of_node = pdev->dev.of_node; 441 436 442 437 if (spi_ingenic_request_dma(ctlr, dev)) ··· 461 452 .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17), 462 453 .flen_field = REG_FIELD(REG_SSICR1, 4, 7), 463 454 .has_trendian = false, 455 + 456 + .max_speed_hz = 54000000, 457 + .max_native_cs = 2, 464 458 }; 465 459 466 460 static const struct jz_soc_info jz4780_soc_info = { 467 461 .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), 468 462 .flen_field = REG_FIELD(REG_SSICR1, 3, 7), 469 463 .has_trendian = true, 464 + 465 + .max_speed_hz = 54000000, 466 + .max_native_cs = 2, 467 + }; 468 + 469 + static const struct jz_soc_info x1000_soc_info = { 470 + .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), 471 + .flen_field = REG_FIELD(REG_SSICR1, 3, 7), 472 + .has_trendian = true, 473 + 474 + .max_speed_hz = 50000000, 475 + .max_native_cs = 2, 476 + }; 477 + 478 + static const struct jz_soc_info x2000_soc_info = { 479 + .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32), 480 + .flen_field = REG_FIELD(REG_SSICR1, 3, 7), 481 + .has_trendian = true, 482 + 483 + .max_speed_hz = 50000000, 484 + .max_native_cs = 1, 470 485 }; 471 486 472 487 static const struct of_device_id spi_ingenic_of_match[] = { 473 488 { .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info }, 489 + { .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info }, 474 490 { .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info }, 491 + { .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info }, 492 + { .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info }, 475 493 {} 476 494 }; 477 495 MODULE_DEVICE_TABLE(of, spi_ingenic_of_match); ··· 512 476 }; 513 477 514 478 module_platform_driver(spi_ingenic_driver); 515 - MODULE_DESCRIPTION("SPI bus driver for the Ingenic JZ47xx SoCs"); 479 + MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs"); 516 480 MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>"); 517 481 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 482 + MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>"); 518 483 MODULE_LICENSE("GPL");