tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: mmcc-msm8998: Use ARRAY_SIZE for num_parents

Where possible, use ARRAY_SIZE to determine the number of parents in
clk_parent_data, instead of hardcoding it.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20210911121340.261920-6-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marijn Suijten and committed by
Stephen Boyd 9ee049eb ce336a51

+39 -39
+39 -39
drivers/clk/qcom/mmcc-msm8998.c
··· 518 518 .clkr.hw.init = &(struct clk_init_data){ 519 519 .name = "byte0_clk_src", 520 520 .parent_data = mmss_xo_dsibyte, 521 - .num_parents = 4, 521 + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 522 522 .ops = &clk_byte2_ops, 523 523 .flags = CLK_SET_RATE_PARENT, 524 524 }, ··· 531 531 .clkr.hw.init = &(struct clk_init_data){ 532 532 .name = "byte1_clk_src", 533 533 .parent_data = mmss_xo_dsibyte, 534 - .num_parents = 4, 534 + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 535 535 .ops = &clk_byte2_ops, 536 536 .flags = CLK_SET_RATE_PARENT, 537 537 }, ··· 552 552 .clkr.hw.init = &(struct clk_init_data){ 553 553 .name = "cci_clk_src", 554 554 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div, 555 - .num_parents = 7, 555 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div), 556 556 .ops = &clk_rcg2_ops, 557 557 }, 558 558 }; ··· 576 576 .clkr.hw.init = &(struct clk_init_data){ 577 577 .name = "cpp_clk_src", 578 578 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 579 - .num_parents = 8, 579 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 580 580 .ops = &clk_rcg2_ops, 581 581 }, 582 582 }; ··· 599 599 .clkr.hw.init = &(struct clk_init_data){ 600 600 .name = "csi0_clk_src", 601 601 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 602 - .num_parents = 8, 602 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 603 603 .ops = &clk_rcg2_ops, 604 604 }, 605 605 }; ··· 612 612 .clkr.hw.init = &(struct clk_init_data){ 613 613 .name = "csi1_clk_src", 614 614 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 615 - .num_parents = 8, 615 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 616 616 .ops = &clk_rcg2_ops, 617 617 }, 618 618 }; ··· 625 625 .clkr.hw.init = &(struct clk_init_data){ 626 626 .name = "csi2_clk_src", 627 627 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 628 - .num_parents = 8, 628 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 629 629 .ops = &clk_rcg2_ops, 630 630 }, 631 631 }; ··· 638 638 .clkr.hw.init = &(struct clk_init_data){ 639 639 .name = "csi3_clk_src", 640 640 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 641 - .num_parents = 8, 641 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 642 642 .ops = &clk_rcg2_ops, 643 643 }, 644 644 }; ··· 660 660 .clkr.hw.init = &(struct clk_init_data){ 661 661 .name = "csiphy_clk_src", 662 662 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 663 - .num_parents = 8, 663 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 664 664 .ops = &clk_rcg2_ops, 665 665 }, 666 666 }; ··· 679 679 .clkr.hw.init = &(struct clk_init_data){ 680 680 .name = "csi0phytimer_clk_src", 681 681 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 682 - .num_parents = 8, 682 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 683 683 .ops = &clk_rcg2_ops, 684 684 }, 685 685 }; ··· 692 692 .clkr.hw.init = &(struct clk_init_data){ 693 693 .name = "csi1phytimer_clk_src", 694 694 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 695 - .num_parents = 8, 695 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 696 696 .ops = &clk_rcg2_ops, 697 697 }, 698 698 }; ··· 705 705 .clkr.hw.init = &(struct clk_init_data){ 706 706 .name = "csi2phytimer_clk_src", 707 707 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 708 - .num_parents = 8, 708 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 709 709 .ops = &clk_rcg2_ops, 710 710 }, 711 711 }; ··· 723 723 .clkr.hw.init = &(struct clk_init_data){ 724 724 .name = "dp_aux_clk_src", 725 725 .parent_data = mmss_xo_gpll0_gpll0_div, 726 - .num_parents = 4, 726 + .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 727 727 .ops = &clk_rcg2_ops, 728 728 }, 729 729 }; ··· 743 743 .clkr.hw.init = &(struct clk_init_data){ 744 744 .name = "dp_crypto_clk_src", 745 745 .parent_data = mmss_xo_dp, 746 - .num_parents = 4, 746 + .num_parents = ARRAY_SIZE(mmss_xo_dp), 747 747 .ops = &clk_rcg2_ops, 748 748 }, 749 749 }; ··· 763 763 .clkr.hw.init = &(struct clk_init_data){ 764 764 .name = "dp_link_clk_src", 765 765 .parent_data = mmss_xo_dp, 766 - .num_parents = 4, 766 + .num_parents = ARRAY_SIZE(mmss_xo_dp), 767 767 .ops = &clk_rcg2_ops, 768 768 }, 769 769 }; ··· 783 783 .clkr.hw.init = &(struct clk_init_data){ 784 784 .name = "dp_pixel_clk_src", 785 785 .parent_data = mmss_xo_dp, 786 - .num_parents = 4, 786 + .num_parents = ARRAY_SIZE(mmss_xo_dp), 787 787 .ops = &clk_rcg2_ops, 788 788 }, 789 789 }; ··· 801 801 .clkr.hw.init = &(struct clk_init_data){ 802 802 .name = "esc0_clk_src", 803 803 .parent_data = mmss_xo_dsibyte, 804 - .num_parents = 4, 804 + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 805 805 .ops = &clk_rcg2_ops, 806 806 }, 807 807 }; ··· 814 814 .clkr.hw.init = &(struct clk_init_data){ 815 815 .name = "esc1_clk_src", 816 816 .parent_data = mmss_xo_dsibyte, 817 - .num_parents = 4, 817 + .num_parents = ARRAY_SIZE(mmss_xo_dsibyte), 818 818 .ops = &clk_rcg2_ops, 819 819 }, 820 820 }; ··· 832 832 .clkr.hw.init = &(struct clk_init_data){ 833 833 .name = "extpclk_clk_src", 834 834 .parent_data = mmss_xo_hdmi, 835 - .num_parents = 3, 835 + .num_parents = ARRAY_SIZE(mmss_xo_hdmi), 836 836 .ops = &clk_byte_ops, 837 837 .flags = CLK_SET_RATE_PARENT, 838 838 }, ··· 855 855 .clkr.hw.init = &(struct clk_init_data){ 856 856 .name = "fd_core_clk_src", 857 857 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 858 - .num_parents = 8, 858 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 859 859 .ops = &clk_rcg2_ops, 860 860 }, 861 861 }; ··· 873 873 .clkr.hw.init = &(struct clk_init_data){ 874 874 .name = "hdmi_clk_src", 875 875 .parent_data = mmss_xo_gpll0_gpll0_div, 876 - .num_parents = 4, 876 + .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 877 877 .ops = &clk_rcg2_ops, 878 878 }, 879 879 }; ··· 894 894 .clkr.hw.init = &(struct clk_init_data){ 895 895 .name = "jpeg0_clk_src", 896 896 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 897 - .num_parents = 8, 897 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 898 898 .ops = &clk_rcg2_ops, 899 899 }, 900 900 }; ··· 916 916 .clkr.hw.init = &(struct clk_init_data){ 917 917 .name = "maxi_clk_src", 918 918 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 919 - .num_parents = 6, 919 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 920 920 .ops = &clk_rcg2_ops, 921 921 }, 922 922 }; ··· 943 943 .clkr.hw.init = &(struct clk_init_data){ 944 944 .name = "mclk0_clk_src", 945 945 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 946 - .num_parents = 7, 946 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 947 947 .ops = &clk_rcg2_ops, 948 948 }, 949 949 }; ··· 956 956 .clkr.hw.init = &(struct clk_init_data){ 957 957 .name = "mclk1_clk_src", 958 958 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 959 - .num_parents = 7, 959 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 960 960 .ops = &clk_rcg2_ops, 961 961 }, 962 962 }; ··· 969 969 .clkr.hw.init = &(struct clk_init_data){ 970 970 .name = "mclk2_clk_src", 971 971 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 972 - .num_parents = 7, 972 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 973 973 .ops = &clk_rcg2_ops, 974 974 }, 975 975 }; ··· 982 982 .clkr.hw.init = &(struct clk_init_data){ 983 983 .name = "mclk3_clk_src", 984 984 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 985 - .num_parents = 7, 985 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 986 986 .ops = &clk_rcg2_ops, 987 987 }, 988 988 }; ··· 1008 1008 .clkr.hw.init = &(struct clk_init_data){ 1009 1009 .name = "mdp_clk_src", 1010 1010 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 1011 - .num_parents = 6, 1011 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), 1012 1012 .ops = &clk_rcg2_ops, 1013 1013 }, 1014 1014 }; ··· 1026 1026 .clkr.hw.init = &(struct clk_init_data){ 1027 1027 .name = "vsync_clk_src", 1028 1028 .parent_data = mmss_xo_gpll0_gpll0_div, 1029 - .num_parents = 4, 1029 + .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div), 1030 1030 .ops = &clk_rcg2_ops, 1031 1031 }, 1032 1032 }; ··· 1046 1046 .clkr.hw.init = &(struct clk_init_data){ 1047 1047 .name = "ahb_clk_src", 1048 1048 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, 1049 - .num_parents = 5, 1049 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div), 1050 1050 .ops = &clk_rcg2_ops, 1051 1051 }, 1052 1052 }; ··· 1069 1069 .clkr.hw.init = &(struct clk_init_data){ 1070 1070 .name = "axi_clk_src", 1071 1071 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, 1072 - .num_parents = 6, 1072 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div), 1073 1073 .ops = &clk_rcg2_ops, 1074 1074 }, 1075 1075 }; ··· 1082 1082 .clkr.hw.init = &(struct clk_init_data){ 1083 1083 .name = "pclk0_clk_src", 1084 1084 .parent_data = mmss_xo_dsi0pll_dsi1pll, 1085 - .num_parents = 4, 1085 + .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 1086 1086 .ops = &clk_pixel_ops, 1087 1087 .flags = CLK_SET_RATE_PARENT, 1088 1088 }, ··· 1096 1096 .clkr.hw.init = &(struct clk_init_data){ 1097 1097 .name = "pclk1_clk_src", 1098 1098 .parent_data = mmss_xo_dsi0pll_dsi1pll, 1099 - .num_parents = 4, 1099 + .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll), 1100 1100 .ops = &clk_pixel_ops, 1101 1101 .flags = CLK_SET_RATE_PARENT, 1102 1102 }, ··· 1118 1118 .clkr.hw.init = &(struct clk_init_data){ 1119 1119 .name = "rot_clk_src", 1120 1120 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, 1121 - .num_parents = 6, 1121 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div), 1122 1122 .ops = &clk_rcg2_ops, 1123 1123 }, 1124 1124 }; ··· 1140 1140 .clkr.hw.init = &(struct clk_init_data){ 1141 1141 .name = "video_core_clk_src", 1142 1142 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1143 - .num_parents = 7, 1143 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1144 1144 .ops = &clk_rcg2_ops, 1145 1145 }, 1146 1146 }; ··· 1153 1153 .clkr.hw.init = &(struct clk_init_data){ 1154 1154 .name = "video_subcore0_clk_src", 1155 1155 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1156 - .num_parents = 7, 1156 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1157 1157 .ops = &clk_rcg2_ops, 1158 1158 }, 1159 1159 }; ··· 1166 1166 .clkr.hw.init = &(struct clk_init_data){ 1167 1167 .name = "video_subcore1_clk_src", 1168 1168 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, 1169 - .num_parents = 7, 1169 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div), 1170 1170 .ops = &clk_rcg2_ops, 1171 1171 }, 1172 1172 }; ··· 1191 1191 .clkr.hw.init = &(struct clk_init_data){ 1192 1192 .name = "vfe0_clk_src", 1193 1193 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 1194 - .num_parents = 8, 1194 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 1195 1195 .ops = &clk_rcg2_ops, 1196 1196 }, 1197 1197 }; ··· 1204 1204 .clkr.hw.init = &(struct clk_init_data){ 1205 1205 .name = "vfe1_clk_src", 1206 1206 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, 1207 - .num_parents = 8, 1207 + .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div), 1208 1208 .ops = &clk_rcg2_ops, 1209 1209 }, 1210 1210 };