tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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PCI: use dev_printk in x86 quirk messages

Convert quirk printks to dev_printk().

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>


authored by

bjorn.helgaas@hp.com and committed by
Greg Kroah-Hartman 9ed88554 f0fda801

+34 -31
unified split
+23 -20
arch/x86/kernel/quirks.c
··· 30 30 raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word); 31 31 32 32 if (!(word & (1 << 13))) { 33 - printk(KERN_INFO "Intel E7520/7320/7525 detected. " 34 - "Disabling irq balancing and affinity\n"); 33 + dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " 34 + "disabling irq balancing and affinity\n"); 35 35 #ifdef CONFIG_IRQBALANCE 36 36 irqbalance_disable(""); 37 37 #endif ··· 104 104 pci_read_config_dword(dev, 0xF0, &rcba); 105 105 rcba &= 0xFFFFC000; 106 106 if (rcba == 0) { 107 - printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n"); 107 + dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " 108 + "cannot force enable HPET\n"); 108 109 return; 109 110 } 110 111 111 112 /* use bits 31:14, 16 kB aligned */ 112 113 rcba_base = ioremap_nocache(rcba, 0x4000); 113 114 if (rcba_base == NULL) { 114 - printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n"); 115 + dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " 116 + "cannot force enable HPET\n"); 115 117 return; 116 118 } 117 119 ··· 124 122 /* HPET is enabled in HPTC. Just not reported by BIOS */ 125 123 val = val & 0x3; 126 124 force_hpet_address = 0xFED00000 | (val << 12); 127 - printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", 128 - force_hpet_address); 125 + dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 126 + "0x%lx\n", force_hpet_address); 129 127 iounmap(rcba_base); 130 128 return; 131 129 } ··· 144 142 if (err) { 145 143 force_hpet_address = 0; 146 144 iounmap(rcba_base); 147 - printk(KERN_DEBUG "Failed to force enable HPET\n"); 145 + dev_printk(KERN_DEBUG, &dev->dev, 146 + "Failed to force enable HPET\n"); 148 147 } else { 149 148 force_hpet_resume_type = ICH_FORCE_HPET_RESUME; 150 - printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", 151 - force_hpet_address); 149 + dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 150 + "0x%lx\n", force_hpet_address); 152 151 } 153 152 } 154 153 ··· 211 208 if (val & 0x4) { 212 209 val &= 0x3; 213 210 force_hpet_address = 0xFED00000 | (val << 12); 214 - printk(KERN_DEBUG "HPET at base address 0x%lx\n", 215 - force_hpet_address); 211 + dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", 212 + force_hpet_address); 216 213 return; 217 214 } 218 215 ··· 232 229 /* HPET is enabled in HPTC. Just not reported by BIOS */ 233 230 val &= 0x3; 234 231 force_hpet_address = 0xFED00000 | (val << 12); 235 - printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", 236 - force_hpet_address); 232 + dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 233 + "0x%lx\n", force_hpet_address); 237 234 cached_dev = dev; 238 235 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; 239 236 return; 240 237 } 241 238 242 - printk(KERN_DEBUG "Failed to force enable HPET\n"); 239 + dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); 243 240 } 244 241 245 242 /* ··· 297 294 */ 298 295 if (val & 0x80) { 299 296 force_hpet_address = (val & ~0x3ff); 300 - printk(KERN_DEBUG "HPET at base address 0x%lx\n", 301 - force_hpet_address); 297 + dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", 298 + force_hpet_address); 302 299 return; 303 300 } 304 301 ··· 312 309 pci_read_config_dword(dev, 0x68, &val); 313 310 if (val & 0x80) { 314 311 force_hpet_address = (val & ~0x3ff); 315 - printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", 316 - force_hpet_address); 312 + dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " 313 + "0x%lx\n", force_hpet_address); 317 314 cached_dev = dev; 318 315 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; 319 316 return; 320 317 } 321 318 322 - printk(KERN_DEBUG "Failed to force enable HPET\n"); 319 + dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); 323 320 } 324 321 325 322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, ··· 347 344 pci_read_config_dword(dev, 0x44, &val); 348 345 force_hpet_address = val & 0xfffffffe; 349 346 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; 350 - printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n", 347 + dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", 351 348 force_hpet_address); 352 349 cached_dev = dev; 353 350 return;
+11 -11
arch/x86/pci/fixup.c
··· 17 17 int pxb, reg; 18 18 u8 busno, suba, subb; 19 19 20 - printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d)); 20 + dev_warn(&d->dev, "Searching for i450NX host bridges\n"); 21 21 reg = 0xd0; 22 22 for(pxb = 0; pxb < 2; pxb++) { 23 23 pci_read_config_byte(d, reg++, &busno); ··· 41 41 */ 42 42 u8 busno; 43 43 pci_read_config_byte(d, 0x4a, &busno); 44 - printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno); 44 + dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); 45 45 pci_scan_bus_with_sysdata(busno); 46 46 pcibios_last_bus = -1; 47 47 } ··· 55 55 */ 56 56 int i; 57 57 58 - printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d)); 58 + dev_warn(&d->dev, "Fixing base address flags\n"); 59 59 for(i = 0; i < 4; i++) 60 60 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; 61 61 } ··· 68 68 * Fix class to be PCI_CLASS_STORAGE_SCSI 69 69 */ 70 70 if (!d->class) { 71 - printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d)); 71 + dev_warn(&d->dev, "Fixing NCR 53C810 class code\n"); 72 72 d->class = PCI_CLASS_STORAGE_SCSI << 8; 73 73 } 74 74 } ··· 80 80 * SiS 5597 and 5598 chipsets require latency timer set to 81 81 * at most 32 to avoid lockups. 82 82 */ 83 - DBG("PCI: Setting max latency to 32\n"); 83 + dev_dbg(&d->dev, "Setting max latency to 32\n"); 84 84 pcibios_max_latency = 32; 85 85 } 86 86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); ··· 138 138 139 139 pci_read_config_byte(d, where, &v); 140 140 if (v & ~mask) { 141 - printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ 141 + dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ 142 142 d->device, d->revision, where, v, mask, v & mask); 143 143 v &= mask; 144 144 pci_write_config_byte(d, where, v); ··· 200 200 * Apply fixup if needed, but don't touch disconnect state 201 201 */ 202 202 if ((val & 0x00FF0000) != 0x00010000) { 203 - printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n"); 203 + dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); 204 204 pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); 205 205 } 206 206 } ··· 348 348 pci_read_config_word(pdev, PCI_COMMAND, &config); 349 349 if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 350 350 pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW; 351 - printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev)); 351 + dev_printk(KERN_DEBUG, &pdev->dev, "Boot video device\n"); 352 352 } 353 353 } 354 354 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video); ··· 388 388 /* verify the change for status output */ 389 389 pci_read_config_byte(dev, 0x50, &val); 390 390 if (val & 0x40) 391 - printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, " 391 + dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 392 392 "can't enable onboard soundcard!\n"); 393 393 else 394 - printk(KERN_INFO "PCI: Detected MSI K8T Neo2-FIR, " 395 - "enabled onboard soundcard.\n"); 394 + dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " 395 + "enabled onboard soundcard\n"); 396 396 } 397 397 } 398 398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,