tjh.dev / kernel
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drm/amdgpu: Add mqd for userq compute queue

Add mqd for userq compute queue for gfx11/gfx12

Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Arunpravin Paneer Selvam and committed by
Alex Deucher 9ed335d9 31f7efcd

+12 -4
+4
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 4312 4312 4313 4313 mqd->cp_hqd_active = prop->hqd_active; 4314 4314 4315 + /* set UQ fenceaddress */ 4316 + mqd->fence_address_lo = lower_32_bits(prop->fence_address); 4317 + mqd->fence_address_hi = upper_32_bits(prop->fence_address); 4318 + 4315 4319 return 0; 4316 4320 } 4317 4321
+4
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
··· 3215 3215 3216 3216 mqd->cp_hqd_active = prop->hqd_active; 3217 3217 3218 + /* set UQ fenceaddress */ 3219 + mqd->fence_address_lo = lower_32_bits(prop->fence_address); 3220 + mqd->fence_address_hi = upper_32_bits(prop->fence_address); 3221 + 3218 3222 return 0; 3219 3223 } 3220 3224
+2 -2
drivers/gpu/drm/amd/include/v11_structs.h
··· 1118 1118 uint32_t reserved_443; // offset: 443 (0x1BB) 1119 1119 uint32_t reserved_444; // offset: 444 (0x1BC) 1120 1120 uint32_t reserved_445; // offset: 445 (0x1BD) 1121 - uint32_t reserved_446; // offset: 446 (0x1BE) 1122 - uint32_t reserved_447; // offset: 447 (0x1BF) 1121 + uint32_t fence_address_lo; // offset: 446 (0x1BE) 1122 + uint32_t fence_address_hi; // offset: 447 (0x1BF) 1123 1123 uint32_t gws_0_val; // offset: 448 (0x1C0) 1124 1124 uint32_t gws_1_val; // offset: 449 (0x1C1) 1125 1125 uint32_t gws_2_val; // offset: 450 (0x1C2)
+2 -2
drivers/gpu/drm/amd/include/v12_structs.h
··· 1118 1118 uint32_t reserved_443; // offset: 443 (0x1BB) 1119 1119 uint32_t reserved_444; // offset: 444 (0x1BC) 1120 1120 uint32_t reserved_445; // offset: 445 (0x1BD) 1121 - uint32_t reserved_446; // offset: 446 (0x1BE) 1122 - uint32_t reserved_447; // offset: 447 (0x1BF) 1121 + uint32_t fence_address_lo; // offset: 446 (0x1BE) 1122 + uint32_t fence_address_hi; // offset: 447 (0x1BF) 1123 1123 uint32_t gws_0_val; // offset: 448 (0x1C0) 1124 1124 uint32_t gws_1_val; // offset: 449 (0x1C1) 1125 1125 uint32_t gws_2_val; // offset: 450 (0x1C2)